;; Copyright Model Technology, a Mentor Graphics Corporation company 2004,; All rights reserved.;[Library]std = $MODEL_TECH/../stdieee = $MODEL_TECH/../ieeeverilog = $MODEL_TECH/../verilogvital2000 = $MODEL_TECH/../vital2000std_developerskit = $MODEL_TECH/../std_developerskitsynopsys = $MODEL_TECH/../synopsysmodelsim_lib = $MODEL_TECH/../modelsim_libwork = workaltera_220 = C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/220model[vcom]; VHDL93 variable selects language version as the default. ; Default is VHDL-2002.; Value of 0 or 1987 for VHDL-1987.; Value of 1 or 1993 for VHDL-1993.; Default or value of 2 or 2002 for VHDL-2002.VHDL93 = 2002; Show source line containing error. Default is off.; Show_source = 1; Turn off unbound-component warnings. Default is on.; Show_Warning1 = 0; Turn off process-without-a-wait-statement warnings. Default is on.; Show_Warning2 = 0; Turn off null-range warnings. Default is on.; Show_Warning3 = 0; Turn off no-space-in-time-literal warnings. Default is on.; Show_Warning4 = 0; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.; Show_Warning5 = 0; Turn off optimization for IEEE std_logic_1164 package. Default is on.; Optimize_1164 = 0; Turn on resolving of ambiguous function overloading in favor of the; "explicit" function declaration (not the one automatically created by; the compiler for each type declaration). Default is off.; The .ini file has Explict enabled so that std_logic_signed/unsigned; will match the behavior of synthesis tools.Explicit = 1; Turn off acceleration of the VITAL packages. Default is to accelerate.; NoVital = 1; Turn off VITAL compliance checking. Default is checking on.; NoVitalCheck = 1; Ignore VITAL compliance checking errors. Default is to not ignore.; IgnoreVitalErrors = 1; Turn off VITAL compliance checking warnings. Default is to show warnings.; Show_VitalChecksWarnings = 0; Turn off PSL assertion warning messges. Default is to show warnings.; Show_PslChecksWarnings = 0; Enable parsing of embedded PSL assertions. Default is enabled.; EmbeddedPsl = 0; Keep silent about case statement static warnings.; Default is to give a warning.; NoCaseStaticError = 1; Keep silent about warnings caused by aggregates that are not locally static.; Default is to give a warning.; NoOthersStaticError = 1; Treat as errors:;   case statement static warnings;   warnings caused by aggregates that are not locally static; Overrides NoCaseStaticError, NoOthersStaticError settings.; PedanticErrors = 1; Turn off inclusion of debugging info within design units.; Default is to include debugging info.; NoDebug = 1; Turn off "Loading..." messages. Default is messages on.; Quiet = 1; Turn on some limited synthesis rule compliance checking. Checks only:;    -- signals used (read) by a process must be in the sensitivity list; CheckSynthesis = 1; Activate optimizations on expressions that do not involve signals,; waits, or function/procedure/task invocations. Default is off.; ScalarOpts = 1; Require the user to specify a configuration for all bindings,; and do not generate a compile time default binding for the; component. This will result in an elaboration error of; 'component not bound' if the user fails to do so. Avoids the rare; issue of a false dependency upon the unused default binding.; RequireConfigForAllDefaultBinding = 1; Inhibit range checking on subscripts of arrays. Range checking on; scalars defined with subtypes is inhibited by default.; NoIndexCheck = 1; Inhibit range checks on all (implicit and explicit) assignments to; scalar objects defined with subtypes.; NoRangeCheck = 1[vlog]; Turn off inclusion of debugging info within design units.; Default is to include debugging info.; NoDebug = 1; Turn on `protect compiler directive processing.; Default is to ignore `protect directives.; Protect = 1; Turn off "Loading..." messages. Default is messages on.; Quiet = 1; Turn on Verilog hazard checking (order-dependent accessing of global vars).; Default is off.; Hazard = 1; Turn on converting regular Verilog identifiers to uppercase. Allows case; insensitivity for module names. Default is no conversion.; UpCase = 1; Turn on incremental compilation of modules. Default is off.; Incremental = 1; Activate optimizations on expressions that do not involve signals,; waits, or function/procedure/task invocations. Default is off.; ScalarOpts = 1; Turns on lint-style checking.; Show_Lint = 1; Show source line containing error. Default is off.; Show_source = 1; Turn on bad option warning. Default is off.; Show_BadOptionWarning = 1; Revert back to IEEE 1364-1995 syntax, default is 0 (off).vlog95compat = 0[sccom]; Disable SystemC name binding during compilation. Default is off.; NoNameBind = 1; Enable use of SCV include files and library.  Default is off.; UseScv = 1; Add C++ compiler options to the sccom command line by using this variable.; CppOptions = -g; Use custom C++ compiler located at this path rather than ModelSim default.; The path should point directly at a compiler executable.; CppPath = /usr/bin/g++; Enable verbose messages from sccom.  Default is off.; SccomVerbose = 1; sccom logfile.  Default is no logfile.; SccomLogfile = sccom.log[vsim]; Simulator resolution; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.resolution = 1ns; User time unit for run commands; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the; unit specified for Resolution. For example, if Resolution is 100ps,; then UserTimeUnit defaults to ps.; Should generally be set to default.UserTimeUnit = ns; Default run lengthRunLength = 100 ns; Maximum iterations that can be run without advancing simulation timeIterationLimit = 5000; Directives to license manager can be set either as single value or as; space separated multi-values:; vhdl          Immediately reserve a VHDL license; vlog          Immediately reserve a Verilog license; plus          Immediately reserve a VHDL and Verilog license; nomgc         Do not look for Mentor Graphics Licenses; nomti         Do not look for Model Technology Licenses; noqueue       Do not wait in the license queue when a license is not available; viewsim       Try for viewer license but accept simulator license(s) instead;               of queuing for viewer license (PE ONLY); Single value:; License = plus; Multi-value:; License = noqueue plus; Stop the simulator after a VHDL assertion message; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = FatalBreakOnAssertion = 3; VHDL assertion Message Format; %S - Severity Level ; %R - Report Message; %T - Time of assertion; %D - Delta; %I - Instance or Region pathname (if available); %i - Instance pathname with process; %O - Process name; %K - Kind of object path is to return: Instance, Signal, Process or Unknown; %P - Instance or Region path without leaf process; %F - File; %L - Line number of assertion or, if assertion is in a subprogram, line;      from which the call is made; %% - Print '%' character; If specific format for assertion level is defined, use its format.; If specific format is not define for assertion level, use AssertionFormatBreak; if assertion triggers a breakpoint (controlled by BreakOnAssertion level),; otherwise use AssertionFormat.;; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"