--F1_q_b[0] is dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[0] at M4K_X37_Y29
F1_q_b[0]_PORT_A_data_in = BUS(data_in[0], data_in[1], data_in[2], data_in[3], data_in[4], data_in[5], data_in[6], data_in[7]);
F1_q_b[0]_PORT_A_data_in_reg = DFFE(F1_q_b[0]_PORT_A_data_in, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_A_address = BUS(H1_safe_q[0], H1_safe_q[1], H1_safe_q[2], H1_safe_q[3], H1_safe_q[4]);
F1_q_b[0]_PORT_A_address_reg = DFFE(F1_q_b[0]_PORT_A_address, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_B_address = BUS(rd_addr[0], rd_addr[1], rd_addr[2], rd_addr[3], rd_addr[4]);
F1_q_b[0]_PORT_B_address_reg = DFFE(F1_q_b[0]_PORT_B_address, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_A_write_enable = wr_en;
F1_q_b[0]_PORT_A_write_enable_reg = DFFE(F1_q_b[0]_PORT_A_write_enable, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_B_read_enable = rd_en;
F1_q_b[0]_PORT_B_read_enable_reg = DFFE(F1_q_b[0]_PORT_B_read_enable, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_clock_0 = GLOBAL(G1__clk0);
F1_q_b[0]_clear_0 = !GLOBAL(rst);
F1_q_b[0]_PORT_B_data_out = MEMORY(F1_q_b[0]_PORT_A_data_in_reg, , F1_q_b[0]_PORT_A_address_reg, F1_q_b[0]_PORT_B_address_reg, F1_q_b[0]_PORT_A_write_enable_reg, F1_q_b[0]_PORT_B_read_enable_reg, , , F1_q_b[0]_clock_0, , , , F1_q_b[0]_clear_0, );
F1_q_b[0]_PORT_B_data_out_reg = DFFE(F1_q_b[0]_PORT_B_data_out, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0] = F1_q_b[0]_PORT_B_data_out_reg[0];

--F1_q_b[7] is dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[7] at M4K_X37_Y29
F1_q_b[0]_PORT_A_data_in = BUS(data_in[0], data_in[1], data_in[2], data_in[3], data_in[4], data_in[5], data_in[6], data_in[7]);
F1_q_b[0]_PORT_A_data_in_reg = DFFE(F1_q_b[0]_PORT_A_data_in, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_A_address = BUS(H1_safe_q[0], H1_safe_q[1], H1_safe_q[2], H1_safe_q[3], H1_safe_q[4]);
F1_q_b[0]_PORT_A_address_reg = DFFE(F1_q_b[0]_PORT_A_address, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_B_address = BUS(rd_addr[0], rd_addr[1], rd_addr[2], rd_addr[3], rd_addr[4]);
F1_q_b[0]_PORT_B_address_reg = DFFE(F1_q_b[0]_PORT_B_address, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_A_write_enable = wr_en;
F1_q_b[0]_PORT_A_write_enable_reg = DFFE(F1_q_b[0]_PORT_A_write_enable, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_B_read_enable = rd_en;
F1_q_b[0]_PORT_B_read_enable_reg = DFFE(F1_q_b[0]_PORT_B_read_enable, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_clock_0 = GLOBAL(G1__clk0);
F1_q_b[0]_clear_0 = !GLOBAL(rst);
F1_q_b[0]_PORT_B_data_out = MEMORY(F1_q_b[0]_PORT_A_data_in_reg, , F1_q_b[0]_PORT_A_address_reg, F1_q_b[0]_PORT_B_address_reg, F1_q_b[0]_PORT_A_write_enable_reg, F1_q_b[0]_PORT_B_read_enable_reg, , , F1_q_b[0]_clock_0, , , , F1_q_b[0]_clear_0, );
F1_q_b[0]_PORT_B_data_out_reg = DFFE(F1_q_b[0]_PORT_B_data_out, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[7] = F1_q_b[0]_PORT_B_data_out_reg[7];

--F1_q_b[6] is dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[6] at M4K_X37_Y29
F1_q_b[0]_PORT_A_data_in = BUS(data_in[0], data_in[1], data_in[2], data_in[3], data_in[4], data_in[5], data_in[6], data_in[7]);
F1_q_b[0]_PORT_A_data_in_reg = DFFE(F1_q_b[0]_PORT_A_data_in, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_A_address = BUS(H1_safe_q[0], H1_safe_q[1], H1_safe_q[2], H1_safe_q[3], H1_safe_q[4]);
F1_q_b[0]_PORT_A_address_reg = DFFE(F1_q_b[0]_PORT_A_address, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_B_address = BUS(rd_addr[0], rd_addr[1], rd_addr[2], rd_addr[3], rd_addr[4]);
F1_q_b[0]_PORT_B_address_reg = DFFE(F1_q_b[0]_PORT_B_address, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_A_write_enable = wr_en;
F1_q_b[0]_PORT_A_write_enable_reg = DFFE(F1_q_b[0]_PORT_A_write_enable, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_B_read_enable = rd_en;
F1_q_b[0]_PORT_B_read_enable_reg = DFFE(F1_q_b[0]_PORT_B_read_enable, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_clock_0 = GLOBAL(G1__clk0);
F1_q_b[0]_clear_0 = !GLOBAL(rst);
F1_q_b[0]_PORT_B_data_out = MEMORY(F1_q_b[0]_PORT_A_data_in_reg, , F1_q_b[0]_PORT_A_address_reg, F1_q_b[0]_PORT_B_address_reg, F1_q_b[0]_PORT_A_write_enable_reg, F1_q_b[0]_PORT_B_read_enable_reg, , , F1_q_b[0]_clock_0, , , , F1_q_b[0]_clear_0, );
F1_q_b[0]_PORT_B_data_out_reg = DFFE(F1_q_b[0]_PORT_B_data_out, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[6] = F1_q_b[0]_PORT_B_data_out_reg[6];

--F1_q_b[5] is dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[5] at M4K_X37_Y29
F1_q_b[0]_PORT_A_data_in = BUS(data_in[0], data_in[1], data_in[2], data_in[3], data_in[4], data_in[5], data_in[6], data_in[7]);
F1_q_b[0]_PORT_A_data_in_reg = DFFE(F1_q_b[0]_PORT_A_data_in, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_A_address = BUS(H1_safe_q[0], H1_safe_q[1], H1_safe_q[2], H1_safe_q[3], H1_safe_q[4]);
F1_q_b[0]_PORT_A_address_reg = DFFE(F1_q_b[0]_PORT_A_address, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_B_address = BUS(rd_addr[0], rd_addr[1], rd_addr[2], rd_addr[3], rd_addr[4]);
F1_q_b[0]_PORT_B_address_reg = DFFE(F1_q_b[0]_PORT_B_address, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_A_write_enable = wr_en;
F1_q_b[0]_PORT_A_write_enable_reg = DFFE(F1_q_b[0]_PORT_A_write_enable, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_B_read_enable = rd_en;
F1_q_b[0]_PORT_B_read_enable_reg = DFFE(F1_q_b[0]_PORT_B_read_enable, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_clock_0 = GLOBAL(G1__clk0);
F1_q_b[0]_clear_0 = !GLOBAL(rst);
F1_q_b[0]_PORT_B_data_out = MEMORY(F1_q_b[0]_PORT_A_data_in_reg, , F1_q_b[0]_PORT_A_address_reg, F1_q_b[0]_PORT_B_address_reg, F1_q_b[0]_PORT_A_write_enable_reg, F1_q_b[0]_PORT_B_read_enable_reg, , , F1_q_b[0]_clock_0, , , , F1_q_b[0]_clear_0, );
F1_q_b[0]_PORT_B_data_out_reg = DFFE(F1_q_b[0]_PORT_B_data_out, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[5] = F1_q_b[0]_PORT_B_data_out_reg[5];

--F1_q_b[4] is dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[4] at M4K_X37_Y29
F1_q_b[0]_PORT_A_data_in = BUS(data_in[0], data_in[1], data_in[2], data_in[3], data_in[4], data_in[5], data_in[6], data_in[7]);
F1_q_b[0]_PORT_A_data_in_reg = DFFE(F1_q_b[0]_PORT_A_data_in, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_A_address = BUS(H1_safe_q[0], H1_safe_q[1], H1_safe_q[2], H1_safe_q[3], H1_safe_q[4]);
F1_q_b[0]_PORT_A_address_reg = DFFE(F1_q_b[0]_PORT_A_address, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_B_address = BUS(rd_addr[0], rd_addr[1], rd_addr[2], rd_addr[3], rd_addr[4]);
F1_q_b[0]_PORT_B_address_reg = DFFE(F1_q_b[0]_PORT_B_address, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_A_write_enable = wr_en;
F1_q_b[0]_PORT_A_write_enable_reg = DFFE(F1_q_b[0]_PORT_A_write_enable, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_B_read_enable = rd_en;
F1_q_b[0]_PORT_B_read_enable_reg = DFFE(F1_q_b[0]_PORT_B_read_enable, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_clock_0 = GLOBAL(G1__clk0);
F1_q_b[0]_clear_0 = !GLOBAL(rst);
F1_q_b[0]_PORT_B_data_out = MEMORY(F1_q_b[0]_PORT_A_data_in_reg, , F1_q_b[0]_PORT_A_address_reg, F1_q_b[0]_PORT_B_address_reg, F1_q_b[0]_PORT_A_write_enable_reg, F1_q_b[0]_PORT_B_read_enable_reg, , , F1_q_b[0]_clock_0, , , , F1_q_b[0]_clear_0, );
F1_q_b[0]_PORT_B_data_out_reg = DFFE(F1_q_b[0]_PORT_B_data_out, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[4] = F1_q_b[0]_PORT_B_data_out_reg[4];

--F1_q_b[3] is dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[3] at M4K_X37_Y29
F1_q_b[0]_PORT_A_data_in = BUS(data_in[0], data_in[1], data_in[2], data_in[3], data_in[4], data_in[5], data_in[6], data_in[7]);
F1_q_b[0]_PORT_A_data_in_reg = DFFE(F1_q_b[0]_PORT_A_data_in, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_A_address = BUS(H1_safe_q[0], H1_safe_q[1], H1_safe_q[2], H1_safe_q[3], H1_safe_q[4]);
F1_q_b[0]_PORT_A_address_reg = DFFE(F1_q_b[0]_PORT_A_address, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_B_address = BUS(rd_addr[0], rd_addr[1], rd_addr[2], rd_addr[3], rd_addr[4]);
F1_q_b[0]_PORT_B_address_reg = DFFE(F1_q_b[0]_PORT_B_address, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_A_write_enable = wr_en;
F1_q_b[0]_PORT_A_write_enable_reg = DFFE(F1_q_b[0]_PORT_A_write_enable, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_B_read_enable = rd_en;
F1_q_b[0]_PORT_B_read_enable_reg = DFFE(F1_q_b[0]_PORT_B_read_enable, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_clock_0 = GLOBAL(G1__clk0);
F1_q_b[0]_clear_0 = !GLOBAL(rst);
F1_q_b[0]_PORT_B_data_out = MEMORY(F1_q_b[0]_PORT_A_data_in_reg, , F1_q_b[0]_PORT_A_address_reg, F1_q_b[0]_PORT_B_address_reg, F1_q_b[0]_PORT_A_write_enable_reg, F1_q_b[0]_PORT_B_read_enable_reg, , , F1_q_b[0]_clock_0, , , , F1_q_b[0]_clear_0, );
F1_q_b[0]_PORT_B_data_out_reg = DFFE(F1_q_b[0]_PORT_B_data_out, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[3] = F1_q_b[0]_PORT_B_data_out_reg[3];

--F1_q_b[2] is dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[2] at M4K_X37_Y29
F1_q_b[0]_PORT_A_data_in = BUS(data_in[0], data_in[1], data_in[2], data_in[3], data_in[4], data_in[5], data_in[6], data_in[7]);
F1_q_b[0]_PORT_A_data_in_reg = DFFE(F1_q_b[0]_PORT_A_data_in, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_A_address = BUS(H1_safe_q[0], H1_safe_q[1], H1_safe_q[2], H1_safe_q[3], H1_safe_q[4]);
F1_q_b[0]_PORT_A_address_reg = DFFE(F1_q_b[0]_PORT_A_address, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_B_address = BUS(rd_addr[0], rd_addr[1], rd_addr[2], rd_addr[3], rd_addr[4]);
F1_q_b[0]_PORT_B_address_reg = DFFE(F1_q_b[0]_PORT_B_address, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_A_write_enable = wr_en;
F1_q_b[0]_PORT_A_write_enable_reg = DFFE(F1_q_b[0]_PORT_A_write_enable, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_B_read_enable = rd_en;
F1_q_b[0]_PORT_B_read_enable_reg = DFFE(F1_q_b[0]_PORT_B_read_enable, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_clock_0 = GLOBAL(G1__clk0);
F1_q_b[0]_clear_0 = !GLOBAL(rst);
F1_q_b[0]_PORT_B_data_out = MEMORY(F1_q_b[0]_PORT_A_data_in_reg, , F1_q_b[0]_PORT_A_address_reg, F1_q_b[0]_PORT_B_address_reg, F1_q_b[0]_PORT_A_write_enable_reg, F1_q_b[0]_PORT_B_read_enable_reg, , , F1_q_b[0]_clock_0, , , , F1_q_b[0]_clear_0, );
F1_q_b[0]_PORT_B_data_out_reg = DFFE(F1_q_b[0]_PORT_B_data_out, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[2] = F1_q_b[0]_PORT_B_data_out_reg[2];

--F1_q_b[1] is dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[1] at M4K_X37_Y29
F1_q_b[0]_PORT_A_data_in = BUS(data_in[0], data_in[1], data_in[2], data_in[3], data_in[4], data_in[5], data_in[6], data_in[7]);
F1_q_b[0]_PORT_A_data_in_reg = DFFE(F1_q_b[0]_PORT_A_data_in, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_A_address = BUS(H1_safe_q[0], H1_safe_q[1], H1_safe_q[2], H1_safe_q[3], H1_safe_q[4]);
F1_q_b[0]_PORT_A_address_reg = DFFE(F1_q_b[0]_PORT_A_address, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_B_address = BUS(rd_addr[0], rd_addr[1], rd_addr[2], rd_addr[3], rd_addr[4]);
F1_q_b[0]_PORT_B_address_reg = DFFE(F1_q_b[0]_PORT_B_address, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_A_write_enable = wr_en;
F1_q_b[0]_PORT_A_write_enable_reg = DFFE(F1_q_b[0]_PORT_A_write_enable, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_PORT_B_read_enable = rd_en;
F1_q_b[0]_PORT_B_read_enable_reg = DFFE(F1_q_b[0]_PORT_B_read_enable, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[0]_clock_0 = GLOBAL(G1__clk0);
F1_q_b[0]_clear_0 = !GLOBAL(rst);
F1_q_b[0]_PORT_B_data_out = MEMORY(F1_q_b[0]_PORT_A_data_in_reg, , F1_q_b[0]_PORT_A_address_reg, F1_q_b[0]_PORT_B_address_reg, F1_q_b[0]_PORT_A_write_enable_reg, F1_q_b[0]_PORT_B_read_enable_reg, , , F1_q_b[0]_clock_0, , , , F1_q_b[0]_clear_0, );
F1_q_b[0]_PORT_B_data_out_reg = DFFE(F1_q_b[0]_PORT_B_data_out, F1_q_b[0]_clock_0, F1_q_b[0]_clear_0, , );
F1_q_b[1] = F1_q_b[0]_PORT_B_data_out_reg[1];


--G1__locked is pllx2:pllx2_u1|altpll:altpll_component|_locked at PLL_5
G1__locked = PLL.LOCKED(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(!GLOBAL(rst)), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(clk_in), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());

--G1__clk0 is pllx2:pllx2_u1|altpll:altpll_component|_clk0 at PLL_5
G1__clk0 = PLL.CLK0(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(!GLOBAL(rst)), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(clk_in), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());


--H1_safe_q[4] is lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[4] at LC_X39_Y29_N9
--operation mode is normal

H1_safe_q[4]_lut_out = H1_safe_q[4] $ (wr_en & !H1L22);
H1_safe_q[4] = DFFEA(H1_safe_q[4]_lut_out, GLOBAL(G1__clk0), GLOBAL(rst), , , , );


--H1_safe_q[3] is lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[3] at LC_X39_Y29_N8
--operation mode is arithmetic

H1_safe_q[3]_lut_out = H1_safe_q[3] $ (wr_en & H1L91);
H1_safe_q[3] = DFFEA(H1_safe_q[3]_lut_out, GLOBAL(G1__clk0), GLOBAL(rst), , , , );

--H1L22 is lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[3]~COUT0 at LC_X39_Y29_N8
--operation mode is arithmetic

H1L22_cout_0 = !H1L91 # !H1_safe_q[3];
H1L22 = CARRY(H1L22_cout_0);

--H1L32 is lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[3]~COUT1 at LC_X39_Y29_N8
--operation mode is arithmetic

H1L32_cout_1 = !H1L02 # !H1_safe_q[3];
H1L32 = CARRY(H1L32_cout_1);


--H1_safe_q[2] is lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[2] at LC_X39_Y29_N7
--operation mode is arithmetic

H1_safe_q[2]_lut_out = H1_safe_q[2] $ (wr_en & !H1L61);
H1_safe_q[2] = DFFEA(H1_safe_q[2]_lut_out, GLOBAL(G1__clk0), GLOBAL(rst), , , , );

--H1L91 is lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[2]~COUT0 at LC_X39_Y29_N7
--operation mode is arithmetic

H1L91_cout_0 = H1_safe_q[2] & !H1L61;
H1L91 = CARRY(H1L91_cout_0);

--H1L02 is lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[2]~COUT1 at LC_X39_Y29_N7
--operation mode is arithmetic

H1L02_cout_1 = H1_safe_q[2] & !H1L71;
H1L02 = CARRY(H1L02_cout_1);


--H1_safe_q[1] is lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] at LC_X39_Y29_N6
--operation mode is arithmetic

H1_safe_q[1]_lut_out = H1_safe_q[1] $ (wr_en & H1L31);
H1_safe_q[1] = DFFEA(H1_safe_q[1]_lut_out, GLOBAL(G1__clk0), GLOBAL(rst), , , , );

--H1L61 is lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1]~COUT0 at LC_X39_Y29_N6
--operation mode is arithmetic

H1L61_cout_0 = !H1L31 # !H1_safe_q[1];
H1L61 = CARRY(H1L61_cout_0);

--H1L71 is lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1]~COUT1 at LC_X39_Y29_N6
--operation mode is arithmetic

H1L71_cout_1 = !H1L41 # !H1_safe_q[1];
H1L71 = CARRY(H1L71_cout_1);