?? pll_ram.fit.rpt
字號(hào):
Fitter report for pll_ram
Sun Dec 05 05:42:57 2004
Version 4.0 Build 190 1/28/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Fitter Device Options
5. Fitter Equations
6. Floorplan View
7. Pin-Out File
8. Fitter Resource Usage Summary
9. Input Pins
10. Output Pins
11. I/O Bank Usage
12. All Package Pins
13. PLL Summary
14. PLL Usage
15. Output Pin Load For Reported TCO
16. Fitter Resource Utilization by Entity
17. Delay Chain Summary
18. Pad To Core Delay Chain Fanout
19. Control Signals
20. Global & Other Fast Signals
21. Non-Global High Fan-Out Signals
22. Fitter RAM Summary
23. Interconnect Usage Summary
24. LAB Logic Elements
25. LAB-wide Signals
26. LAB Signals Sourced
27. LAB Signals Sourced Out
28. LAB Distinct Inputs
29. Fitter Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+------------------------------------------------------------------+
; Fitter Summary ;
+--------------------------+---------------------------------------+
; Fitter Status ; Successful - Sun Dec 05 05:42:57 2004 ;
; Revision Name ; pll_ram ;
; Top-level Entity Name ; pll_ram ;
; Family ; Stratix ;
; Device ; EP1S10B672C6 ;
; Total logic elements ; 8 / 10,570 ( < 1 % ) ;
; Total pins ; 28 / 346 ( 8 % ) ;
; Total memory bits ; 256 / 920,448 ( < 1 % ) ;
; DSP block 9-bit elements ; 0 / 48 ( 0 % ) ;
; Total PLLs ; 1 / 6 ( 16 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
+--------------------------+---------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Option ; Setting ; Default Value ;
+------------------------------------------------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device ; EP1S10B672C6 ; ;
; Auto Register Duplication ; Off ; Off ;
; Logic Cell Insertion -- Logic Duplication ; Auto ; Auto ;
; Perform physical synthesis with extra effort; uses extra compile time to try for extra circuit performance ; Off ; Off ;
; Perform Register Retiming ; Off ; Off ;
; Perform Register Duplication ; Off ; Off ;
; Perform Physical Synthesis for Combinational Logic ; Off ; Off ;
; Auto Merge PLLs ; On ; On ;
; Auto Delay Chains ; On ; On ;
; Auto Packed Registers -- Stratix/Stratix GX ; Normal ; Normal ;
; Auto Global Memory Control Signals ; Off ; Off ;
; Enable Bus-Hold Circuitry ; Off ; Off ;
; Weak Pull-Up Resistor ; Off ; Off ;
; PCI I/O ; Off ; Off ;
; Slow Slew Rate ; Off ; Off ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; Final Placement Optimizations ; Automatically ; Automatically ;
; FIT_ONLY_ONE_ATTEMPT ; Off ; Off ;
; Optimize IOC Register Placement for Timing ; On ; On ;
; Optimize Timing ; Normal Compilation ; Normal Compilation ;
; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
+------------------------------------------------------------------------------------------------------------+--------------------------------+--------------------------------+
+-------------------------------------------------------------------------+
; Fitter Device Options ;
+--------------------------------------------------------------------------
; Option ; Setting ;
+----------------------------------------------+--------------------------+
?? 快捷鍵說(shuō)明
復(fù)制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號(hào)
Ctrl + =
減小字號(hào)
Ctrl + -