{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "after " "Info: Details of I/O bank after I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.30V 26 13 " "Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 26 total pin(s) used --  13 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 39 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  39 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 1 42 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  42 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 1 44 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  44 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use unused 1 38 " "Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  38 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use unused 0 39 " "Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  39 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use unused 0 45 " "Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  45 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use unused 0 44 " "Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  44 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use unused 0 6 " "Info: I/O bank number 9 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "10 does not use unused 0 0 " "Info: I/O bank number 10 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "11 does not use unused 0 6 " "Info: I/O bank number 11 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "12 does not use unused 0 0 " "Info: I/O bank number 12 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Warning" "WCUT_CUT_YGR_PLL_BAD_FANOUT_CLK3" "clk0 pllx2:pllx2_u1\|altpll:altpll_component\|pll " "Warning: Output port clk0 of PLL pllx2:pllx2_u1\|altpll:altpll_component\|pll feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance." {  } { { "c:/eda/quartus/libraries/megafunctions/altpll.tdf" "" "" { Text "c:/eda/quartus/libraries/megafunctions/altpll.tdf" 652 3 0 } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.284 ns memory memory " "Info: Estimated most critical path is memory to memory delay of 3.284 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dpram8x32:dpram8x32_u1\|altsyncram:altsyncram_component\|altsyncram_7bc1:auto_generated\|ram_block1a0~porta_datain_reg0 1 MEM M4K_X37_Y29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X37_Y29; Fanout = 1; MEM Node = 'dpram8x32:dpram8x32_u1\|altsyncram:altsyncram_component\|altsyncram_7bc1:auto_generated\|ram_block1a0~porta_datain_reg0'" {  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/db/altsyncram_7bc1.tdf" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/db/altsyncram_7bc1.tdf" 43 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.284 ns) 3.284 ns dpram8x32:dpram8x32_u1\|altsyncram:altsyncram_component\|altsyncram_7bc1:auto_generated\|ram_block1a0~porta_memory_reg0 2 MEM M4K_X37_Y29 0 " "Info: 2: + IC(0.000 ns) + CELL(3.284 ns) = 3.284 ns; Loc. = M4K_X37_Y29; Fanout = 0; MEM Node = 'dpram8x32:dpram8x32_u1\|altsyncram:altsyncram_component\|altsyncram_7bc1:auto_generated\|ram_block1a0~porta_memory_reg0'" {  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "3.284 ns" { dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg0 dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/db/altsyncram_7bc1.tdf" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/db/altsyncram_7bc1.tdf" 43 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.284 ns 100.00 % " "Info: Total cell delay = 3.284 ns ( 100.00 % )" {  } {  } 0}  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "3.284 ns" { dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg0 dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Estimated interconnect usage is 1% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "1 " "Info: Fitter placement operations ending: elapsed time = 1 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "0 " "Info: Fitter routing operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}