{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 05 05:43:06 2004 " "Info: Processing started: Sun Dec 05 05:43:06 2004" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off pll_ram -c pll_ram --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off pll_ram -c pll_ram --timing_analysis_only" {  } {  } 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 memory dpram8x32:dpram8x32_u1\|altsyncram:altsyncram_component\|altsyncram_7bc1:auto_generated\|ram_block1a0~porta_datain_reg0 memory dpram8x32:dpram8x32_u1\|altsyncram:altsyncram_component\|altsyncram_7bc1:auto_generated\|ram_block1a0~porta_memory_reg0 6.087 ns " "Info: Slack time is 6.087 ns for clock pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 between source memory dpram8x32:dpram8x32_u1\|altsyncram:altsyncram_component\|altsyncram_7bc1:auto_generated\|ram_block1a0~porta_datain_reg0 and destination memory dpram8x32:dpram8x32_u1\|altsyncram:altsyncram_component\|altsyncram_7bc1:auto_generated\|ram_block1a0~porta_memory_reg0" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "255.56 MHz 3.913 ns " "Info: Fmax is 255.56 MHz (period= 3.913 ns)" {  } {  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "9.371 ns + Largest memory memory " "Info: + Largest memory to memory requirement is 9.371 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "10.000 ns + " "Info: + Setup relationship between source and destination is 10.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 7.824 ns " "Info: + Latch edge is 7.824 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 10.000 ns -2.176 ns  50 " "Info: Clock period of Destination clock pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 is 10.000 ns with  offset of -2.176 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.176 ns " "Info: - Launch edge is -2.176 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 10.000 ns -2.176 ns  50 " "Info: Clock period of Source clock pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 is 10.000 ns with  offset of -2.176 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.013 ns + Largest " "Info: + Largest clock skew is -0.013 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 destination 1.858 ns + Shortest memory " "Info: + Shortest clock path from clock pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 to destination memory is 1.858 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 1 CLK PLL_5 42 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_5; Fanout = 42; CLK Node = 'pllx2:pllx2_u1\|altpll:altpll_component\|_clk0'" {  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 } "NODE_NAME" } } } { "c:/eda/quartus/libraries/megafunctions/altpll.tdf" "" "" { Text "c:/eda/quartus/libraries/megafunctions/altpll.tdf" 652 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.302 ns) + CELL(0.556 ns) 1.858 ns dpram8x32:dpram8x32_u1\|altsyncram:altsyncram_component\|altsyncram_7bc1:auto_generated\|ram_block1a0~porta_memory_reg0 2 MEM M4K_X37_Y29 0 " "Info: 2: + IC(1.302 ns) + CELL(0.556 ns) = 1.858 ns; Loc. = M4K_X37_Y29; Fanout = 0; MEM Node = 'dpram8x32:dpram8x32_u1\|altsyncram:altsyncram_component\|altsyncram_7bc1:auto_generated\|ram_block1a0~porta_memory_reg0'" {  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "1.858 ns" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/db/altsyncram_7bc1.tdf" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/db/altsyncram_7bc1.tdf" 43 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.556 ns 29.92 % " "Info: Total cell delay = 0.556 ns ( 29.92 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.302 ns 70.08 % " "Info: Total interconnect delay = 1.302 ns ( 70.08 % )" {  } {  } 0}  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "1.858 ns" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 source 1.871 ns - Longest memory " "Info: - Longest clock path from clock pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 to source memory is 1.871 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 1 CLK PLL_5 42 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_5; Fanout = 42; CLK Node = 'pllx2:pllx2_u1\|altpll:altpll_component\|_clk0'" {  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 } "NODE_NAME" } } } { "c:/eda/quartus/libraries/megafunctions/altpll.tdf" "" "" { Text "c:/eda/quartus/libraries/megafunctions/altpll.tdf" 652 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.302 ns) + CELL(0.569 ns) 1.871 ns dpram8x32:dpram8x32_u1\|altsyncram:altsyncram_component\|altsyncram_7bc1:auto_generated\|ram_block1a0~porta_datain_reg0 2 MEM M4K_X37_Y29 1 " "Info: 2: + IC(1.302 ns) + CELL(0.569 ns) = 1.871 ns; Loc. = M4K_X37_Y29; Fanout = 1; MEM Node = 'dpram8x32:dpram8x32_u1\|altsyncram:altsyncram_component\|altsyncram_7bc1:auto_generated\|ram_block1a0~porta_datain_reg0'" {  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "1.871 ns" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/db/altsyncram_7bc1.tdf" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/db/altsyncram_7bc1.tdf" 43 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.569 ns 30.41 % " "Info: Total cell delay = 0.569 ns ( 30.41 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.302 ns 69.59 % " "Info: Total interconnect delay = 1.302 ns ( 69.59 % )" {  } {  } 0}  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "1.871 ns" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } }  } 0}  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "1.858 ns" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "1.871 ns" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.467 ns - " "Info: - Micro clock to output delay of source is 0.467 ns" {  } { { "d:/prj_d/modelsim_demo/pll_ram/db/altsyncram_7bc1.tdf" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/db/altsyncram_7bc1.tdf" 43 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.149 ns - " "Info: - Micro setup delay of destination is 0.149 ns" {  } { { "d:/prj_d/modelsim_demo/pll_ram/db/altsyncram_7bc1.tdf" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/db/altsyncram_7bc1.tdf" 43 2 0 } }  } 0}  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "1.858 ns" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "1.871 ns" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.284 ns - Longest memory memory " "Info: - Longest memory to memory delay is 3.284 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dpram8x32:dpram8x32_u1\|altsyncram:altsyncram_component\|altsyncram_7bc1:auto_generated\|ram_block1a0~porta_datain_reg0 1 MEM M4K_X37_Y29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X37_Y29; Fanout = 1; MEM Node = 'dpram8x32:dpram8x32_u1\|altsyncram:altsyncram_component\|altsyncram_7bc1:auto_generated\|ram_block1a0~porta_datain_reg0'" {  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/db/altsyncram_7bc1.tdf" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/db/altsyncram_7bc1.tdf" 43 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.284 ns) 3.284 ns dpram8x32:dpram8x32_u1\|altsyncram:altsyncram_component\|altsyncram_7bc1:auto_generated\|ram_block1a0~porta_memory_reg0 2 MEM M4K_X37_Y29 0 " "Info: 2: + IC(0.000 ns) + CELL(3.284 ns) = 3.284 ns; Loc. = M4K_X37_Y29; Fanout = 0; MEM Node = 'dpram8x32:dpram8x32_u1\|altsyncram:altsyncram_component\|altsyncram_7bc1:auto_generated\|ram_block1a0~porta_memory_reg0'" {  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "3.284 ns" { dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg0 dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/db/altsyncram_7bc1.tdf" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/db/altsyncram_7bc1.tdf" 43 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.284 ns 100.00 % " "Info: Total cell delay = 3.284 ns ( 100.00 % )" {  } {  } 0}  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "3.284 ns" { dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg0 dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } }  } 0}  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "1.858 ns" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "1.871 ns" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg0 } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "3.284 ns" { dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg0 dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_memory_reg0 } "NODE_NAME" } } }  } 0}