{ "Info" "ITAN_NO_REG2REG_EXIST" "clk_in " "Info: No valid register-to-register paths exist for clock clk_in" {  } {  } 0}
{ "Info" "ITDB_TSU_RESULT" "lpm_counter:wr_addr_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[0\] wr_en clk_in 6.369 ns register " "Info: tsu for register lpm_counter:wr_addr_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[0\] (data pin = wr_en, clock pin = clk_in) is 6.369 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.027 ns + Longest pin register " "Info: + Longest pin to register delay is 6.027 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.976 ns) 0.976 ns wr_en 1 PIN Pin_F19 6 " "Info: 1: + IC(0.000 ns) + CELL(0.976 ns) = 0.976 ns; Loc. = Pin_F19; Fanout = 6; PIN Node = 'wr_en'" {  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { wr_en } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.468 ns) + CELL(0.583 ns) 6.027 ns lpm_counter:wr_addr_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[0\] 2 REG LC_X39_Y29_N5 5 " "Info: 2: + IC(4.468 ns) + CELL(0.583 ns) = 6.027 ns; Loc. = LC_X39_Y29_N5; Fanout = 5; REG Node = 'lpm_counter:wr_addr_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[0\]'" {  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "5.051 ns" { wr_en lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0] } "NODE_NAME" } } } { "c:/eda/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "c:/eda/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.559 ns 25.87 % " "Info: Total cell delay = 1.559 ns ( 25.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.468 ns 74.13 % " "Info: Total interconnect delay = 4.468 ns ( 74.13 % )" {  } {  } 0}  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "6.027 ns" { wr_en lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "c:/eda/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "c:/eda/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_FULL_PLL_OFFSET" "clk_in pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 -2.176 ns - " "Info: - Offset between input clock clk_in and output clock pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 is -2.176 ns" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 13 -1 0 } } { "c:/eda/quartus/libraries/megafunctions/altpll.tdf" "" "" { Text "c:/eda/quartus/libraries/megafunctions/altpll.tdf" 652 3 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 destination 1.844 ns - Shortest register " "Info: - Shortest clock path from clock pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 to destination register is 1.844 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 1 CLK PLL_5 42 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_5; Fanout = 42; CLK Node = 'pllx2:pllx2_u1\|altpll:altpll_component\|_clk0'" {  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 } "NODE_NAME" } } } { "c:/eda/quartus/libraries/megafunctions/altpll.tdf" "" "" { Text "c:/eda/quartus/libraries/megafunctions/altpll.tdf" 652 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.284 ns) + CELL(0.560 ns) 1.844 ns lpm_counter:wr_addr_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[0\] 2 REG LC_X39_Y29_N5 5 " "Info: 2: + IC(1.284 ns) + CELL(0.560 ns) = 1.844 ns; Loc. = LC_X39_Y29_N5; Fanout = 5; REG Node = 'lpm_counter:wr_addr_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[0\]'" {  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "1.844 ns" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0] } "NODE_NAME" } } } { "c:/eda/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "c:/eda/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns 30.37 % " "Info: Total cell delay = 0.560 ns ( 30.37 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.284 ns 69.63 % " "Info: Total interconnect delay = 1.284 ns ( 69.63 % )" {  } {  } 0}  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "1.844 ns" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0] } "NODE_NAME" } } }  } 0}  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "6.027 ns" { wr_en lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0] } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "1.844 ns" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_in package_full lpm_counter:wr_addr_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[1\] 5.732 ns register " "Info: tco from clock clk_in to destination pin package_full through register lpm_counter:wr_addr_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[1\] is 5.732 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "clk_in pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 -2.176 ns + " "Info: + Offset between input clock clk_in and output clock pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 is -2.176 ns" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 13 -1 0 } } { "c:/eda/quartus/libraries/megafunctions/altpll.tdf" "" "" { Text "c:/eda/quartus/libraries/megafunctions/altpll.tdf" 652 3 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 source 1.844 ns + Longest register " "Info: + Longest clock path from clock pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 to source register is 1.844 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 1 CLK PLL_5 42 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_5; Fanout = 42; CLK Node = 'pllx2:pllx2_u1\|altpll:altpll_component\|_clk0'" {  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 } "NODE_NAME" } } } { "c:/eda/quartus/libraries/megafunctions/altpll.tdf" "" "" { Text "c:/eda/quartus/libraries/megafunctions/altpll.tdf" 652 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.284 ns) + CELL(0.560 ns) 1.844 ns lpm_counter:wr_addr_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[1\] 2 REG LC_X39_Y29_N6 5 " "Info: 2: + IC(1.284 ns) + CELL(0.560 ns) = 1.844 ns; Loc. = LC_X39_Y29_N6; Fanout = 5; REG Node = 'lpm_counter:wr_addr_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[1\]'" {  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "1.844 ns" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] } "NODE_NAME" } } } { "c:/eda/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "c:/eda/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns 30.37 % " "Info: Total cell delay = 0.560 ns ( 30.37 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.284 ns 69.63 % " "Info: Total interconnect delay = 1.284 ns ( 69.63 % )" {  } {  } 0}  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "1.844 ns" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" {  } { { "c:/eda/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "c:/eda/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.888 ns + Longest register pin " "Info: + Longest register to pin delay is 5.888 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:wr_addr_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[1\] 1 REG LC_X39_Y29_N6 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X39_Y29_N6; Fanout = 5; REG Node = 'lpm_counter:wr_addr_rtl_0\|alt_counter_stratix:wysi_counter\|safe_q\[1\]'" {  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] } "NODE_NAME" } } } { "c:/eda/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "" "" { Text "c:/eda/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 316 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.670 ns) + CELL(0.459 ns) 1.129 ns i~24 2 COMB LC_X39_Y29_N4 1 " "Info: 2: + IC(0.670 ns) + CELL(0.459 ns) = 1.129 ns; Loc. = LC_X39_Y29_N4; Fanout = 1; COMB Node = 'i~24'" {  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "1.129 ns" { lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] i~24 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.351 ns) + CELL(0.087 ns) 1.567 ns i~1 3 COMB LC_X39_Y29_N3 1 " "Info: 3: + IC(0.351 ns) + CELL(0.087 ns) = 1.567 ns; Loc. = LC_X39_Y29_N3; Fanout = 1; COMB Node = 'i~1'" {  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "0.438 ns" { i~24 i~1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.563 ns) + CELL(2.758 ns) 5.888 ns package_full 4 PIN Pin_E21 0 " "Info: 4: + IC(1.563 ns) + CELL(2.758 ns) = 5.888 ns; Loc. = Pin_E21; Fanout = 0; PIN Node = 'package_full'" {  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "4.321 ns" { i~1 package_full } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.304 ns 56.11 % " "Info: Total cell delay = 3.304 ns ( 56.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.584 ns 43.89 % " "Info: Total interconnect delay = 2.584 ns ( 43.89 % )" {  } {  } 0}  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "5.888 ns" { lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] i~24 i~1 package_full } "NODE_NAME" } } }  } 0}  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "1.844 ns" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "5.888 ns" { lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] i~24 i~1 package_full } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "dpram8x32:dpram8x32_u1\|altsyncram:altsyncram_component\|altsyncram_7bc1:auto_generated\|q_b\[0\] rst clk_in -3.133 ns memory " "Info: th for memory dpram8x32:dpram8x32_u1\|altsyncram:altsyncram_component\|altsyncram_7bc1:auto_generated\|q_b\[0\] (data pin = rst, clock pin = clk_in) is -3.133 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "clk_in pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 -2.176 ns + " "Info: + Offset between input clock clk_in and output clock pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 is -2.176 ns" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 13 -1 0 } } { "c:/eda/quartus/libraries/megafunctions/altpll.tdf" "" "" { Text "c:/eda/quartus/libraries/megafunctions/altpll.tdf" 652 3 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 destination 1.858 ns + Longest memory " "Info: + Longest clock path from clock pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 to destination memory is 1.858 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 1 CLK PLL_5 42 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_5; Fanout = 42; CLK Node = 'pllx2:pllx2_u1\|altpll:altpll_component\|_clk0'" {  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 } "NODE_NAME" } } } { "c:/eda/quartus/libraries/megafunctions/altpll.tdf" "" "" { Text "c:/eda/quartus/libraries/megafunctions/altpll.tdf" 652 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.302 ns) + CELL(0.556 ns) 1.858 ns dpram8x32:dpram8x32_u1\|altsyncram:altsyncram_component\|altsyncram_7bc1:auto_generated\|q_b\[0\] 2 MEM M4K_X37_Y29 1 " "Info: 2: + IC(1.302 ns) + CELL(0.556 ns) = 1.858 ns; Loc. = M4K_X37_Y29; Fanout = 1; MEM Node = 'dpram8x32:dpram8x32_u1\|altsyncram:altsyncram_component\|altsyncram_7bc1:auto_generated\|q_b\[0\]'" {  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "1.858 ns" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[0] } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/db/altsyncram_7bc1.tdf" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/db/altsyncram_7bc1.tdf" 38 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.556 ns 29.92 % " "Info: Total cell delay = 0.556 ns ( 29.92 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.302 ns 70.08 % " "Info: Total interconnect delay = 1.302 ns ( 70.08 % )" {  } {  } 0}  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "1.858 ns" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.038 ns + " "Info: + Micro hold delay of destination is 0.038 ns" {  } { { "d:/prj_d/modelsim_demo/pll_ram/db/altsyncram_7bc1.tdf" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/db/altsyncram_7bc1.tdf" 38 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.853 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 2.853 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns rst 1 PIN Pin_M24 28 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 28; PIN Node = 'rst'" {  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { rst } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.683 ns) + CELL(0.508 ns) 2.853 ns dpram8x32:dpram8x32_u1\|altsyncram:altsyncram_component\|altsyncram_7bc1:auto_generated\|q_b\[0\] 2 MEM M4K_X37_Y29 1 " "Info: 2: + IC(1.683 ns) + CELL(0.508 ns) = 2.853 ns; Loc. = M4K_X37_Y29; Fanout = 1; MEM Node = 'dpram8x32:dpram8x32_u1\|altsyncram:altsyncram_component\|altsyncram_7bc1:auto_generated\|q_b\[0\]'" {  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "2.191 ns" { rst dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[0] } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/db/altsyncram_7bc1.tdf" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/db/altsyncram_7bc1.tdf" 38 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.170 ns 41.01 % " "Info: Total cell delay = 1.170 ns ( 41.01 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.683 ns 58.99 % " "Info: Total interconnect delay = 1.683 ns ( 58.99 % )" {  } {  } 0}  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "2.853 ns" { rst dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[0] } "NODE_NAME" } } }  } 0}  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "1.858 ns" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[0] } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "2.853 ns" { rst dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk_in clk_out pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 2.399 ns clock " "Info: Minimum tco from clock clk_in to destination pin clk_out through clock pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 is 2.399 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "clk_in pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 -2.176 ns + " "Info: + Offset between input clock clk_in and output clock pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 is -2.176 ns" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 13 -1 0 } } { "c:/eda/quartus/libraries/megafunctions/altpll.tdf" "" "" { Text "c:/eda/quartus/libraries/megafunctions/altpll.tdf" 652 3 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.575 ns + Shortest clock pin " "Info: + Shortest clock to pin delay is 4.575 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 1 CLK PLL_5 42 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_5; Fanout = 42; CLK Node = 'pllx2:pllx2_u1\|altpll:altpll_component\|_clk0'" {  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 } "NODE_NAME" } } } { "c:/eda/quartus/libraries/megafunctions/altpll.tdf" "" "" { Text "c:/eda/quartus/libraries/megafunctions/altpll.tdf" 652 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.075 ns) + CELL(2.500 ns) 4.575 ns clk_out 2 PIN Pin_P8 0 " "Info: 2: + IC(2.075 ns) + CELL(2.500 ns) = 4.575 ns; Loc. = Pin_P8; Fanout = 0; PIN Node = 'clk_out'" {  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "4.575 ns" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 clk_out } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns 54.64 % " "Info: Total cell delay = 2.500 ns ( 54.64 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.075 ns 45.36 % " "Info: Total interconnect delay = 2.075 ns ( 45.36 % )" {  } {  } 0}  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "4.575 ns" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 clk_out } "NODE_NAME" } } }  } 0}  } { { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "4.575 ns" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 clk_out } "NODE_NAME" } } }  } 0}