{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 05 05:42:27 2004 " "Info: Processing started: Sun Dec 05 05:42:27 2004" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off pll_ram -c pll_ram " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off pll_ram -c pll_ram" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "pll_ram EP1S10B672C6 " "Info: Selected device EP1S10B672C6 for design pll_ram" {  } {  } 0}
{ "Info" "IFYGR_FYGR_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFYGR_FYGR_MIGRATION_NOT_SELECTED_SUB" "EP1S20B672C6 " "Info: Device EP1S20B672C6 is compatible" {  } {  } 2} { "Info" "IFYGR_FYGR_MIGRATION_NOT_SELECTED_SUB" "EP1S25B672C6 " "Info: Device EP1S25B672C6 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "28 28 " "Info: No exact pin location assignment(s) for 28 pins of 28 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "clk_out " "Info: Pin clk_out not assigned to an exact location on the device" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 20 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_out" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { clk_out } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { clk_out } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "lock " "Info: Pin lock not assigned to an exact location on the device" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 21 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "lock" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { lock } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { lock } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "package_full " "Info: Pin package_full not assigned to an exact location on the device" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 22 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "package_full" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { package_full } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { package_full } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_out\[7\] " "Info: Pin data_out\[7\] not assigned to an exact location on the device" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 23 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "data_out\[7\]" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { data_out[7] } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { data_out[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_out\[6\] " "Info: Pin data_out\[6\] not assigned to an exact location on the device" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 23 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "data_out\[6\]" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { data_out[6] } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { data_out[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_out\[5\] " "Info: Pin data_out\[5\] not assigned to an exact location on the device" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 23 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "data_out\[5\]" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { data_out[5] } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { data_out[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_out\[4\] " "Info: Pin data_out\[4\] not assigned to an exact location on the device" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 23 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "data_out\[4\]" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { data_out[4] } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { data_out[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_out\[3\] " "Info: Pin data_out\[3\] not assigned to an exact location on the device" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 23 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "data_out\[3\]" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { data_out[3] } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { data_out[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_out\[2\] " "Info: Pin data_out\[2\] not assigned to an exact location on the device" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 23 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "data_out\[2\]" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { data_out[2] } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { data_out[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_out\[1\] " "Info: Pin data_out\[1\] not assigned to an exact location on the device" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 23 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "data_out\[1\]" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { data_out[1] } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { data_out[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_out\[0\] " "Info: Pin data_out\[0\] not assigned to an exact location on the device" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 23 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "data_out\[0\]" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { data_out[0] } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { data_out[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "rst " "Info: Pin rst not assigned to an exact location on the device" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 14 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "rst" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { rst } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { rst } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "clk_in " "Info: Pin clk_in not assigned to an exact location on the device" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 13 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_in" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { clk_in } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { clk_in } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "wr_en " "Info: Pin wr_en not assigned to an exact location on the device" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 16 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "wr_en" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { wr_en } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { wr_en } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "rd_en " "Info: Pin rd_en not assigned to an exact location on the device" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 17 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "rd_en" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { rd_en } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { rd_en } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[7\] " "Info: Pin data_in\[7\] not assigned to an exact location on the device" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 15 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "data_in\[7\]" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { data_in[7] } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { data_in[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "rd_addr\[0\] " "Info: Pin rd_addr\[0\] not assigned to an exact location on the device" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 18 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "rd_addr\[0\]" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { rd_addr[0] } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { rd_addr[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "rd_addr\[1\] " "Info: Pin rd_addr\[1\] not assigned to an exact location on the device" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 18 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "rd_addr\[1\]" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { rd_addr[1] } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { rd_addr[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "rd_addr\[2\] " "Info: Pin rd_addr\[2\] not assigned to an exact location on the device" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 18 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "rd_addr\[2\]" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { rd_addr[2] } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { rd_addr[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "rd_addr\[3\] " "Info: Pin rd_addr\[3\] not assigned to an exact location on the device" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 18 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "rd_addr\[3\]" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { rd_addr[3] } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { rd_addr[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "rd_addr\[4\] " "Info: Pin rd_addr\[4\] not assigned to an exact location on the device" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 18 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "rd_addr\[4\]" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { rd_addr[4] } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { rd_addr[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[6\] " "Info: Pin data_in\[6\] not assigned to an exact location on the device" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 15 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "data_in\[6\]" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { data_in[6] } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { data_in[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[5\] " "Info: Pin data_in\[5\] not assigned to an exact location on the device" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 15 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "data_in\[5\]" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { data_in[5] } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { data_in[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[4\] " "Info: Pin data_in\[4\] not assigned to an exact location on the device" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 15 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "data_in\[4\]" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { data_in[4] } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { data_in[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[3\] " "Info: Pin data_in\[3\] not assigned to an exact location on the device" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 15 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "data_in\[3\]" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { data_in[3] } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { data_in[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[2\] " "Info: Pin data_in\[2\] not assigned to an exact location on the device" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 15 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "data_in\[2\]" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { data_in[2] } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { data_in[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[1\] " "Info: Pin data_in\[1\] not assigned to an exact location on the device" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 15 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "data_in\[1\]" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { data_in[1] } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { data_in[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[0\] " "Info: Pin data_in\[0\] not assigned to an exact location on the device" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 15 -1 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "data_in\[0\]" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { data_in[0] } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { data_in[0] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on non-logic cell registers with location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO_AND_PHASE_SHIFT" "pllx2:pllx2_u1\|altpll:altpll_component\|pll " "Info: Implementing parameter values for PLL pllx2:pllx2_u1\|altpll:altpll_component\|pll" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 2 1 0 0 " "Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 port" {  } {  } 0}  } { { "c:/eda/quartus/libraries/megafunctions/altpll.tdf" "" "" { Text "c:/eda/quartus/libraries/megafunctions/altpll.tdf" 652 3 0 } }  } 0}
{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK" "pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 " "Info: Promoted signal pllx2:pllx2_u1\|altpll:altpll_component\|_clk0 to use global clock" {  } { { "c:/eda/quartus/libraries/megafunctions/altpll.tdf" "" "" { Text "c:/eda/quartus/libraries/megafunctions/altpll.tdf" 652 3 0 } } { "c:/eda/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "pllx2:pllx2_u1\|altpll:altpll_component\|_clk0" } } } } { "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" "" "" { Report "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram_cmp.qrpt" Compiler "pll_ram" "UNKNOWN" "V1" "d:/prj_d/modelsim_demo/pll_ram/db/pll_ram.quartus_db" { Floorplan "" "" "" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 } "NODE_NAME" } } } { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { Floorplan "d:/prj_d/modelsim_demo/pll_ram/pll_ram.fld" "" "" { pllx2:pllx2_u1|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "PLL Placement Operation " "Info: Completed PLL Placement Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "rst Global clock in Pin M24 " "Info: Automatically promoted signal rst to use Global clock in Pin M24" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 14 -1 0 } }  } 0}