$setuphold (posedge clk &&& reset, datac, 0, 0, datac_viol) ;
        $setuphold (posedge clk &&& reset, sclr, 0, 0, sclr_viol) ;
        $setuphold (posedge clk &&& reset, sload, 0, 0, sload_viol) ;
        $setuphold (posedge clk &&& reset, ena, 0, 0, ena_viol) ;
        
        (posedge clk => (regout +: iregout)) = 0 ;
        (posedge aclr => (regout +: 1'b0)) = (0, 0) ;
        (posedge aload => (regout +: iregout)) = (0, 0) ;
        (datac => regout) = (0, 0) ;
        (posedge clk => (qfbkout +: iregout)) = 0 ;
        (posedge aclr => (qfbkout +: 1'b0)) = (0, 0) ;
        (posedge aload => (qfbkout +: iregout)) = (0, 0) ;
        (datac => qfbkout) = (0, 0) ;
    
    endspecify
   
    initial
    begin
        violation = 0;
        clk_last_value = 'b0;
        if (power_up == "low")
        begin
            iregout <= 'b0;
            ipower_up = 0;
        end
        else if (power_up == "high")
        begin
            iregout <= 'b1;
            ipower_up = 1;
        end

        if (register_cascade_mode == "on")
            icascade_mode = 1;
        else
            icascade_mode = 0;

        if (synch_mode == "on" )
            isynch_mode = 1;
        else
            isynch_mode = 0;

        if (x_on_violation == "on")
            ix_on_violation = 1;
        else
            ix_on_violation = 0;
    end
   
    always @ (regcascin_viol or datain_viol or datac_viol or sclr_viol 
              or sload_viol or ena_viol or clk_per_viol)
    begin
        if (ix_on_violation == 1)
        violation = 1;
    end
   
    always @ (clk_in or idatac or iaclr or posedge iaload 
              or negedge devclrn or negedge devpor or posedge violation)
    begin
        if (violation == 1'b1)
        begin
            violation = 0;
            iregout <= 'bx;
        end
        else
        begin
            if (devpor == 'b0)
            begin
                if (ipower_up == 0) // "low"
                    iregout <= 'b0;
                else if (ipower_up == 1) // "high"
                    iregout <= 'b1;
            end
            else if (devclrn == 'b0)
                iregout <= 'b0;
            else if (iaclr === 'b1) 
                iregout <= 'b0 ;
            else if (iaload === 'b1) 
                iregout <= idatac;
            else if (iena === 'b1 && clk_in === 'b1 && 
                     clk_last_value === 'b0)
            begin
                if (isynch_mode == 1)
                begin
                    if (isclr === 'b1)
                        iregout <= 'b0 ;
                    else if (isload === 'b1)
                        iregout <= idatac;
                    else if (icascade_mode == 1)
                        iregout <= iregcascin;
                    else
                        iregout <= idatain;
                end
                else if (icascade_mode == 1)
                    iregout <= iregcascin;
                else 
                    iregout <= idatain;
            end
        end
        clk_last_value = clk_in;
    end
       
    and (regout, iregout, 1'b1);
    and (qfbkout, iregout, 1'b1);
   
endmodule

///////////////////////////////////////////////////////////////////////////////
//
//                                STRATIX_LCELL
//
///////////////////////////////////////////////////////////////////////////////

`timescale 1 ps/1 ps

module stratix_lcell (
                      clk, 
                      dataa, 
                      datab, 
                      datac, 
                      datad, 
                      aclr, 
                      aload, 
                      sclr,
                      sload,
                      ena,
                      cin,
                      cin0,
                      cin1,
                      inverta,
                      regcascin,
                      devclrn,
                      devpor,
                      combout,
                      regout,
                      cout, 
                      cout0,
                      cout1
                     );

input dataa;
input datab;
input datac;
input datad;
input clk; 
input aclr; 
input aload; 
input sclr; 
input sload; 
input ena; 
input cin;
input cin0;
input cin1;
input inverta;
input regcascin;
input devclrn;
input devpor ;

output combout;
output regout;
output cout;
output cout0;
output cout1;

parameter operation_mode = "normal" ;
parameter synch_mode = "off";
parameter register_cascade_mode = "off";
parameter sum_lutc_input = "datac";
parameter lut_mask = "ffff" ;
parameter power_up = "low";
parameter cin_used = "false";
parameter cin0_used = "false";
parameter cin1_used = "false";
parameter output_mode = "comb_only";
parameter lpm_type = "stratix_lcell";
parameter x_on_violation = "on";
   
wire dffin, qfbkin;
   
stratix_asynch_lcell lecomb (
                             .dataa(dataa),
                             .datab(datab), 
                             .datac(datac),
                             .datad(datad),
                             .cin(cin),
                             .cin0(cin0),
                             .cin1(cin1), 
                             .inverta(inverta),
                             .qfbkin(qfbkin),
                             .regin(dffin),
                             .combout(combout),
                             .cout(cout),
                             .cout0(cout0),
                             .cout1(cout1)
                            );
    defparam lecomb.operation_mode = operation_mode;
    defparam lecomb.sum_lutc_input = sum_lutc_input;
    defparam lecomb.cin_used = cin_used;
    defparam lecomb.cin0_used = cin0_used;
    defparam lecomb.cin1_used = cin1_used;
    defparam lecomb.lut_mask = lut_mask;
   
stratix_lcell_register lereg (
                              .clk(clk),
                              .aclr(aclr),
                              .aload(aload),
                              .sclr(sclr),
                              .sload(sload),
                              .ena(ena), 
                              .datain(dffin), 
                              .datac(datac),
                              .regcascin(regcascin),
                              .devclrn(devclrn),
                              .devpor(devpor), 
                              .regout(regout),
                              .qfbkout(qfbkin)
                             );
    defparam lereg.synch_mode = synch_mode;
    defparam lereg.register_cascade_mode = register_cascade_mode;
    defparam lereg.power_up = power_up;
    defparam lereg.x_on_violation = x_on_violation;
   
endmodule



///////////////////////////////////////////////////////////////////////////////
//
//                              STRATIX_ASYNCH_IO
//
///////////////////////////////////////////////////////////////////////////////

`timescale 1 ps/1 ps

  module stratix_asynch_io 
    (
     datain, 
     oe, 
     regin, 
     ddioregin, 
     padio, 
     delayctrlin, 
     combout, 
     regout, 
     ddioregout,
     dqsundelayedout
     );
   
   input datain;
   input oe;
   input regin;
   input ddioregin;
   input delayctrlin;
   output combout;
   output regout;
   output ddioregout;
   output dqsundelayedout;
   inout  padio;
   
   parameter operation_mode = "input";
   parameter bus_hold = "false";
   parameter open_drain_output = "false";
   parameter phase_shift = "0";
   parameter input_frequency = "10000 ps";
   
   reg 	     prev_value;
   
   reg 	     tmp_padio, tmp_combout;
   reg 	     buf_control;
   reg 	     combout_tmp;
   
   reg [1:0] iop_mode;
   
   integer   dqs_delay;
   
   buf(datain_in, datain);
   buf(oe_in, oe);
   buf (delayctrlin_ipd, delayctrlin);
   
   tri 	     padio_tmp;
   
   // convert string to integer with sign
   function integer str2int; 
      input [8*16:1] s;
      
      reg [8*16:1] reg_s;
      reg [8:1] digit;
      reg [8:1] tmp;
      integer m, magnitude;
      integer sign;
      
      begin
         sign = 1;
         magnitude = 0;
         reg_s = s;
         for (m=1; m<=16; m=m+1)
           begin
              tmp = reg_s[128:121];
              digit = tmp & 8'b00001111;
              reg_s = reg_s << 8;
              // Accumulate ascii digits 0-9 only.
              if ((tmp>=48) && (tmp<=57)) 
                magnitude = (magnitude * 10) + digit;
              if (tmp == 45)
                sign = -1;  // Found a '-' character, i.e. number is negative.
           end
         str2int = sign*magnitude;
      end
   endfunction
   
   specify
      (padio => combout) = (0,0);
      (padio => dqsundelayedout) = (0,0);
      (datain => padio) = (0, 0);
      (posedge oe => (padio +: padio_tmp)) = (0, 0);
      (negedge oe => (padio +: 1'bz)) = (0, 0);
      (ddioregin => ddioregout) = (0, 0);
      (regin => regout) = (0, 0);
   endspecify
   
   initial
     begin
	prev_value = 'b0;
	tmp_padio = 'bz;
	dqs_delay = (str2int(phase_shift) * str2int(input_frequency))/360;
	if (operation_mode == "input")
          iop_mode = 0;
	else if (operation_mode == "output")
          iop_mode = 1;
	else if (operation_mode == "bidir")
          iop_mode = 2;
	else
	  begin
	     $display ("Error: Invalid operation_mode specified\n");
	     iop_mode = 3;
	  end
     end
   
   always @(delayctrlin_ipd)
     begin
	if (delayctrlin_ipd == 1'b1)
          dqs_delay = (str2int(phase_shift) * str2int(input_frequency))/360;
	else if (delayctrlin_ipd == 1'b0)
          dqs_delay = 0;
	else begin
           $display($time, " Warning: Illegal value detected on 'delayctrlin' input.");
           dqs_delay = 0;
	end
     end
   
   always @(datain_in or oe_in or padio)
     begin
	if (bus_hold == "true" )
	  begin
	     buf_control = 'b1;
	     if (iop_mode == 1 || iop_mode == 2) // output or bidir
	       begin
		  if ( oe_in == 1)
		    begin
		       if ( open_drain_output == "true" )
			 begin
			    if (datain_in == 0)
			      begin
				 tmp_padio =  1'b0;
				 prev_value = 1'b0;
			      end
			    else if (datain_in == 1'bx)
			      begin
				 tmp_padio = 1'bx;
				 prev_value = 1'bx;
			      end
			    else   // output of tri is 'Z'
			      begin
				 if (iop_mode == 2) // bidir
				   prev_value = padio;
				 tmp_padio = 1'bz;
			      end
			 end  
		       else  // open drain_output = false;
			 begin
			    tmp_padio = datain_in;
			    prev_value = datain_in;
			 end
		    end   
		  else if ( oe_in == 0 )
		    begin
		       if (iop_mode == 2) // bidir
			 prev_value = padio;
		       tmp_padio = 1'bz;
		    end
		  else   // oe == 'X' 
		    begin
		       tmp_padio = 1'bx;
		       prev_value = 1'bx;
		    end
	       end
	     
	     if (iop_mode == 1) // output
	       tmp_combout = 1'bz;
	     else
	       tmp_combout = padio;
	  end
	else    // bus hold is false
	  begin
	     buf_control = 'b0;
	     if (iop_mode == 0) // input
	       begin
		  tmp_combout = padio;
	       end
	     else if (iop_mode == 1 || iop_mode == 2) // output or bidir
	       begin
		  if (iop_mode  == 2) // bidir
		    tmp_combout = padio;
		  if ( oe_in == 1 )
		    begin
		       if ( open_drain_output == "true" )
			 begin
			    if (datain_in == 0)
			      tmp_padio = 1'b0;
			    else if ( datain_in == 1'bx)
			      tmp_padio = 1'bx;
			    else
			      tmp_padio = 1'bz;
			 end
		       else