?? altera_mf.vhd
字號:
sload_upper_data_latent <= sload_upper_data_full when extra_multiplier_latency >0 else sload_upper_data_reg;
mult_is_saturated <= mult_is_saturated_out when (port_mult_is_saturated = "USED") else '0';
accum_is_saturated <= accum_is_saturated_out when (port_accum_is_saturated = "USED") else '0';
-- Parameter Checking
process
begin
if ((dedicated_multiplier_circuitry /= "AUTO") and
(dedicated_multiplier_circuitry /= "YES") and
(dedicated_multiplier_circuitry /= "NO")) then
assert false
report "Error: The DEDICATED_MULTIPLIER_CIRCUITRY parameter is set to an illegal value."
severity error;
end if;
if (width_result < (width_a + width_b)) then
assert false
report "Error: width_result cannot be less than (width_a + width_b)"
severity error;
end if;
if (width_a <= 0) then
assert false
report "Error: width_a must be greater than 0."
severity error;
end if;
if (width_b <= 0) then
assert false
report "Error: width_b must be greater than 0."
severity error;
end if;
if (width_result <= 0) then
assert false
report "Error: width_result must be greater than 0."
severity error;
end if;
if ((not IS_FAMILY_STRATIXII(intended_device_family)) and
(input_source_a /= "DATAA")) then
assert false
report "Error: The input source for port A are limited to input dataa."
severity error;
end if;
if ((not IS_FAMILY_STRATIXII(intended_device_family)) and
(input_source_b /= "DATAB")) then
assert false
report "Error: The input source for port B are limited to input datab."
severity error;
end if;
if ((not IS_FAMILY_STRATIXII(intended_device_family)) and (multiplier_rounding /= "NO")) then
assert false
report "Error: There is no rounding feature for non-StratixII device."
severity error;
end if;
if ((not IS_FAMILY_STRATIXII(intended_device_family)) and (accumulator_rounding /= "NO")) then
assert false
report "Error: There is no rounding feature for non-StratixII device."
severity error;
end if;
if ((not IS_FAMILY_STRATIXII(intended_device_family)) and (multiplier_saturation /= "NO")) then
assert false
report "Error: There is no saturation feature for non-StratixII device."
severity error;
end if;
if ((not IS_FAMILY_STRATIXII(intended_device_family)) and (accumulator_saturation /= "NO")) then
assert false
report "Error: There is no saturation feature for non-StratixII device."
severity error;
end if;
wait;
end process;
-- ----------------------------------------------------------------------------
-- This process contains 1 register and a combinatorial block (to set mult_a)
-- The signal registered is dataa
--
-- The register has an asynchronous clear and a clock enable signal
-- NOTE: the combinatorial block is trigged if input_reg_a is unregistered and
-- dataa changes value
-- ---------------------------------------------------------------------------
process (clock0, clock1, clock2, clock3, aclr0, aclr1, aclr2, aclr3, dataa)
begin
if (input_reg_a = "UNREGISTERED") then
if (input_source_a = "DATAA") then
mult_a <= dataa;
elsif (input_source_a = "SCANA") then
mult_a <= scanina;
elsif (input_source_a = "VARIABLE") then
if (sourcea = '1') then
mult_a <= dataa;
else
mult_a <= scanina;
end if;
end if;
else
if (((input_aclr_a= "ACLR0") and (aclr0 = '1')) or
((input_aclr_a= "ACLR1") and (aclr1 = '1')) or
((input_aclr_a= "ACLR2") and (aclr2 = '1')) or
((input_aclr_a= "ACLR3") and (aclr3 = '1'))) then
mult_a <= (others => '0');
elsif (((input_reg_a = "CLOCK0") and (clock0= '1') and clock0'event and (ena0 ='1')) or
((input_reg_a = "CLOCK1") and (clock1= '1') and clock1'event and (ena1 ='1')) or
((input_reg_a = "CLOCK2") and (clock2= '1') and clock2'event and (ena2 ='1')) or
((input_reg_a = "CLOCK3") and (clock3= '1') and clock3'event and (ena3 ='1'))) then
if (input_source_a = "DATAA") then
mult_a <= dataa;
elsif (input_source_a = "SCANA") then
mult_a <= scanina;
elsif (input_source_a = "VARIABLE") then
if (sourcea = '1') then
mult_a <= dataa;
else
mult_a <= scanina;
end if;
end if;
end if;
end if;
end process;
-- ----------------------------------------------------------------------------
-- This process contains 1 register and a combinatorial block (to set mult_b)
-- The signal registered is datab
--
-- The register has an asynchronous clear and a clock enable signal
-- NOTE: the combinatorial block is trigged if input_reg_b is unregistered and
-- datab changes value
-- ---------------------------------------------------------------------------
process (clock0, clock1, clock2, clock3, aclr0, aclr1, aclr2, aclr3, datab)
begin
if (input_reg_b = "UNREGISTERED") then
if (input_source_b = "DATAB") then
mult_b <= datab;
elsif (input_source_b = "SCANB") then
mult_b <= scaninb;
elsif (input_source_b = "VARIABLE") then
if (sourceb = '1') then
mult_b <= datab;
else
mult_b <= scaninb;
end if;
end if;
else
if (((input_aclr_b= "ACLR0") and (aclr0 = '1')) or
((input_aclr_b= "ACLR1") and (aclr1 = '1')) or
((input_aclr_b= "ACLR2") and (aclr2 = '1')) or
((input_aclr_b= "ACLR3") and (aclr3 = '1'))) then
mult_b <= (others => '0');
elsif (((input_reg_b = "CLOCK0") and (clock0= '1') and clock0'event and (ena0 ='1')) or
((input_reg_b = "CLOCK1") and (clock1= '1') and clock1'event and (ena1 ='1')) or
((input_reg_b = "CLOCK2") and (clock2= '1') and clock2'event and (ena2 ='1')) or
((input_reg_b = "CLOCK3") and (clock3= '1') and clock3'event and (ena3 ='1'))) then
if (input_source_b = "DATAB") then
mult_b <= datab;
elsif (input_source_b = "SCANB") then
mult_b <= scaninb;
elsif (input_source_b = "VARIABLE") then
if (sourceb = '1') then
mult_b <= datab;
else
mult_b <= scaninb;
end if;
end if;
end if;
end if;
end process;
-- ------------------------------------------------------------------------------
-- This process contains 1 register and a combinatorial block (to set addsub_reg)
-- The signal registered is addnsub
--
-- The register has an asynchronous clear and a clock enable signal
-- NOTE: the combinatorial block is trigged if addnsub_reg is unregistered and
-- addnsub changes value
-- ------------------------------------------------------------------------------
process (clock0, clock1, clock2, clock3, aclr0, aclr1, aclr2, aclr3, addnsub)
begin
if (addnsub_reg = "UNREGISTERED") then
addsub_reg <= addnsub;
else
if (((addnsub_aclr= "ACLR0") and (aclr0 = '1')) or
((addnsub_aclr= "ACLR1") and (aclr1 = '1')) or
((addnsub_aclr= "ACLR2") and (aclr2 = '1')) or
((addnsub_aclr= "ACLR3") and (aclr3 = '1'))) then
addsub_reg <= '0';
elsif (((addnsub_reg = "CLOCK0") and (clock0= '1') and clock0'event and (ena0 ='1')) or
((addnsub_reg = "CLOCK1") and (clock1= '1') and clock1'event and (ena1 ='1')) or
((addnsub_reg = "CLOCK2") and (clock2= '1') and clock2'event and (ena2 ='1')) or
((addnsub_reg = "CLOCK3") and (clock3= '1') and clock3'event and (ena3 ='1'))) then
addsub_reg <= addnsub;
end if;
end if;
end process;
-- ------------------------------------------------------------------------------------
-- This process contains 1 register and a combinatorial block (to set addsub_pipe)
-- The signal registered is addnsub_latent
--
-- The register has an asynchronous clear and a clock enable signal
-- NOTE: the combinatorial block is trigged if addnsub_pipeline_reg is unregistered and
-- addsub_latent changes value
-- ------------------------------------------------------------------------------------
process (clock0, clock1, clock2, clock3, aclr0, aclr1, aclr2, aclr3, addsub_latent)
begin
if (addnsub_pipeline_reg = "UNREGISTERED") then
addsub_pipe <= addsub_latent;
else
if (((addnsub_pipeline_aclr= "ACLR0") and (aclr0 = '1')) or
((addnsub_pipeline_aclr= "ACLR1") and (aclr1 = '1')) or
((addnsub_pipeline_aclr= "ACLR2") and (aclr2 = '1')) or
((addnsub_pipeline_aclr= "ACLR3") and (aclr3 = '1'))) then
addsub_pipe <= '0';
elsif (((addnsub_pipeline_reg = "CLOCK0") and (clock0= '1') and clock0'event and (ena0 ='1')) or
((addnsub_pipeline_reg = "CLOCK1") and (clock1= '1') and clock1'event and (ena1 ='1')) or
((addnsub_pipeline_reg = "CLOCK2") and (clock2= '1') and clock2'event and (ena2 ='1')) or
((addnsub_pipeline_reg = "CLOCK3") and (clock3= '1') and clock3'event and (ena3 ='1'))) then
addsub_pipe <= addsub_latent;
end if;
end if;
end process;
-- ---------------------------------------------------------------------------------
-- This process contains 1 register and a combinatorial block (to set acc_sload_reg)
-- The signal registered is accum_sload
--
-- The register has an asynchronous clear and a clock enable signal
-- NOTE: the combinatorial block is trigged if accum_sload_reg is unregistered and
-- accum_sload changes value
-- ---------------------------------------------------------------------------------
process (clock0, clock1, clock2, clock3, aclr0, aclr1, aclr2, aclr3, accum_sload)
begin
if (accum_sload_reg = "UNREGISTERED") then
acc_sload_reg <= accum_sload;
else
if (((accum_sload_aclr= "ACLR0") and (aclr0 = '1')) or
((accum_sload_aclr= "ACLR1") and (aclr1 = '1')) or
((accum_sload_aclr= "ACLR2") and (aclr2 = '1')) or
((accum_sload_aclr= "ACLR3") and (aclr3 = '1'))) then
acc_sload_reg <= '0';
elsif (((accum_sload_reg = "CLOCK0") and (clock0= '1') and clock0'event and (ena0 ='1')) or
((accum_sload_reg = "CLOCK1") and (clock1= '1') and clock1'event and (ena1 ='1')) or
((accum_sload_reg = "CLOCK2") and (clock2= '1') and clock2'event and (ena2 ='1')) or
((accum_sload_reg = "CLOCK3") and (clock3= '1') and clock3'event and (ena3 ='1'))) then
acc_sload_reg <= accum_sload;
end if;
end if;
end process;
-- ------------------------------------------------------------------------------------
-- This process contains 1 register and a combinatorial block (to set accum_sload_pipe)
-- The signal registered is accum_sload_latent
--
-- The register has an asynchronous clear and a clock enable signal
-- NOTE: the combinatorial block is trigged if accum_sload_pipeline_reg
-- is unregistered and accum_sload_latent changes value
-- ------------------------------------------------------------------------------------
process (clock0, clock1, clock2, clock3, aclr0, aclr1, aclr2, aclr3, accum_sload_latent)
begin
if (accum_sload_pipeline_reg = "UNREGISTERED") then
accum_sload_pipe <= accum_sload_latent;
else
if (((accum_sload_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or
((accum_sload_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or
((accum_sload_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or
((accum_sload_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then
accum_sload_pipe <= '0';
elsif (((accum_sload_pipeline_reg = "CLOCK0") and (clock0 = '1') and clock0'event and (ena0 = '1')) or
((accum_sload_pipeline_reg = "CLOCK1") and (clock1 = '1') and clock1'event and (ena1 = '1')) or
((accum_sload_pipeline_reg = "CLOCK2") and (clock2 = '1') and clock2'event and (ena2 = '1')) or
((accum_sload_pipeline_reg = "CLOCK3") and (clock3 = '1') and clock3'event and (ena3 = '1'))) then
accum_sload_pipe <= accum_sload_latent;
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