?? altera_mf.v
字號:
reg [width_out+1:0] result_full;
reg [width_out+1:0] result_full2;
reg a;
// INTERNAL WIRE DECLARATION
wire [width_out:0] temp_sum_wire;
wire cout;
wire cout_int_wire;
wire cout_delayed_wire;
wire overflow_int_wire;
wire [width_out+1:0] result_int_wire;
// INTERNAL TRI DECLARATION
tri0 aclr_int;
tri0 sign_data_int;
tri0 sload_int;
tri1 clken_int;
tri1 add_sub_int;
// LOCAL INTEGER DECLARATION
integer head;
integer i;
// INITIAL CONSTRUCT BLOCK
initial
begin
// Checking for invalid parameters
if( width_in <= 0 )
begin
$display("Error! Value of width_in parameter must be greater than 0.");
$stop;
end
if( width_out <= 0 )
begin
$display("Error! Value of width_out parameter must be greater than 0.");
$stop;
end
if( extra_latency > width_out )
begin
$display("Info: Value of extra_latency parameter should be lower than width_out parameter for better performance/utilization.");
end
if( width_in > width_out )
begin
$display("Error! Value of width_in parameter should be lower than or equal to width_out.");
$stop;
end
result = 0;
cout_delayed = 0;
overflow = 0;
head = 0;
result_int = 0;
for (i = 0; i <= extra_latency; i = i +1)
begin
result_pipe [i] = 0;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(posedge clock or posedge aclr_int)
begin
if (aclr_int == 1)
begin
result_int = 0;
result = 0;
overflow = 0;
cout_delayed = 0;
for (i = 0; i <= extra_latency; i = i +1)
begin
result_pipe [i] = 0;
end
end
else
begin
if (clken_int == 1)
begin
//get result from output register
if (extra_latency > 0)
begin
result_pipe [head] = {
result_int [width_out+1],
{cout_int_wire, result_int [width_out-1:0]}
};
head = (head + 1) % (extra_latency);
result_full = result_pipe [head];
cout_delayed = result_full [width_out];
result = result_full [width_out-1:0];
overflow = result_full [width_out+1];
end
else
begin
result = temp_sum_wire;
overflow = overflow_int_wire;
end
result_int = {overflow_int_wire, {cout_int_wire, temp_sum_wire [width_out-1:0]}};
end
end
end
always @ (data or cin or add_sub_int or sign_data_int or
result_int_wire [width_out -1:0] or sload_int or aclr_int)
begin
// If asynchronous clear, reset and skip.
if (aclr_int == 1) // asynchronous clear
begin
cout_int = 0;
overflow_int = 0;
end
else
begin
if ((lpm_representation == "SIGNED") || (sign_data_int == 1))
begin
zeropad = (data [width_in-1] ==0) ? 0 : -1;
end
else
begin
zeropad = 0;
end
fb_int = (sload_int == 1'b1) ? 0 : result_int_wire [width_out-1:0];
data_int = {zeropad, data};
if ((add_sub_int == 1) || (sload_int == 1))
begin
cin_int = ((sload_int == 1'b1) ? 0 : ((cin === 1'bz) ? 0 : cin));
temp_sum = fb_int + data_int + cin_int;
cout_int = temp_sum [width_out];
end
else
begin
cin_int = (cin === 1'bz) ? 1 : cin;
borrow = ~cin_int;
temp_sum = fb_int - data_int - borrow;
result_full2 = data_int + borrow;
cout_int = (fb_int >= result_full2) ? 1 : 0;
end
if ((lpm_representation == "SIGNED") || (sign_data_int == 1))
begin
a = (data [width_in-1] ~^ fb_int [width_out-1]) ^ (~add_sub_int);
overflow_int = a & (fb_int [width_out-1] ^ temp_sum[width_out-1]);
end
else
begin
overflow_int = (add_sub_int == 1) ? cout_int : ~cout_int;
end
if (sload_int == 1)
begin
cout_int = !add_sub_int;
overflow_int = 0;
end
end
end
// CONTINOUS ASSIGNMENT
// Get the input data and control signals.
assign sign_data_int = sign_data;
assign sload_int = sload;
assign add_sub_int = add_sub;
assign clken_int = clken;
assign aclr_int = aclr;
assign result_int_wire = result_int;
assign temp_sum_wire = temp_sum;
assign cout_int_wire = cout_int;
assign overflow_int_wire = overflow_int;
assign cout = (extra_latency == 0) ? cout_int_wire : cout_delayed_wire;
assign cout_delayed_wire = cout_delayed;
endmodule // End of altaccumulate
// END OF MODULE
//--------------------------------------------------------------------------
// Module Name : altmult_accum
//
// Description : a*b + x (MAC)
//
// Limitation : Stratix DSP block
//
// Results expected : signed & unsigned, maximum of 3 pipelines(latency) each.
//
//--------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module altmult_accum (dataa,
datab,
scanina,
scaninb,
sourcea,
sourceb,
accum_sload_upper_data,
addnsub,
accum_sload,
signa,
signb,
clock0,
clock1,
clock2,
clock3,
ena0,
ena1,
ena2,
ena3,
aclr0,
aclr1,
aclr2,
aclr3,
result,
overflow,
scanouta,
scanoutb,
mult_round,
mult_saturation,
accum_round,
accum_saturation,
mult_is_saturated,
accum_is_saturated);
// ---------------------
// PARAMETER DECLARATION
// ---------------------
parameter width_a = 1;
parameter width_b = 1;
parameter width_result = 2;
parameter input_reg_a = "CLOCK0";
parameter input_aclr_a = "ACLR3";
parameter input_reg_b = "CLOCK0";
parameter input_aclr_b = "ACLR3";
parameter addnsub_reg = "CLOCK0";
parameter addnsub_aclr = "ACLR3";
parameter addnsub_pipeline_reg = "CLOCK0";
parameter addnsub_pipeline_aclr = "ACLR3";
parameter accum_direction = "ADD";
parameter accum_sload_reg = "CLOCK0";
parameter accum_sload_aclr = "ACLR3";
parameter accum_sload_pipeline_reg = "CLOCK0";
parameter accum_sload_pipeline_aclr = "ACLR3";
parameter representation_a = "UNSIGNED";
parameter sign_reg_a = "CLOCK0";
parameter sign_aclr_a = "ACLR3";
parameter sign_pipeline_reg_a = "CLOCK0";
parameter sign_pipeline_aclr_a = "ACLR3";
parameter representation_b = "UNSIGNED";
parameter sign_reg_b = "CLOCK0";
parameter sign_aclr_b = "ACLR3";
parameter sign_pipeline_reg_b = "CLOCK0";
parameter sign_pipeline_aclr_b = "ACLR3";
parameter multiplier_reg = "CLOCK0";
parameter multiplier_aclr = "ACLR3";
parameter output_reg = "CLOCK0";
parameter output_aclr = "ACLR3";
parameter lpm_type = "altmult_accum";
parameter extra_multiplier_latency = 0;
parameter extra_accumulator_latency = 0;
parameter dedicated_multiplier_circuitry = "AUTO";
parameter dsp_block_balancing = "AUTO";
parameter intended_device_family = "Stratix";
// StratixII related parameter
parameter accum_round_aclr = "ACLR3";
parameter accum_round_pipeline_aclr = "ACLR3";
parameter accum_round_pipeline_reg = "CLOCK0";
parameter accum_round_reg = "CLOCK0";
parameter accum_saturation_aclr = "ACLR3";
parameter accum_saturation_pipeline_aclr = "ACLR3";
parameter accum_saturation_pipeline_reg = "CLOCK0";
parameter accum_saturation_reg = "CLOCK0";
parameter accum_sload_upper_data_aclr = "ACLR3";
parameter accum_sload_upper_data_pipeline_aclr = "ACLR3";
parameter accum_sload_upper_data_pipeline_reg = "CLOCK0";
parameter accum_sload_upper_data_reg = "CLOCK0";
parameter mult_round_aclr = "ACLR3";
parameter mult_round_reg = "CLOCK0";
parameter mult_saturation_aclr = "ACLR3";
parameter mult_saturation_reg = "CLOCK0";
parameter input_source_a = "DATAA";
parameter input_source_b = "DATAB";
parameter width_upper_data = 1;
parameter multiplier_rounding = "NO";
parameter multiplier_saturation = "NO";
parameter accumulator_rounding = "NO";
parameter accumulator_saturation = "NO";
parameter port_mult_is_saturated = "UNUSED";
parameter port_accum_is_saturated = "UNUSED";
// ----------------
// PORT DECLARATION
// ----------------
// data input ports
input [width_a -1 : 0] dataa;
input [width_b -1 : 0] datab;
input [width_a -1 : 0] scanina;
input [width_b -1 : 0] scaninb;
input sourcea;
input sourceb;
input [width_result -1 : width_result - width_upper_data] accum_sload_upper_data;
// control signals
input addnsub;
input accum_sload;
input signa;
input signb;
// clock ports
input clock0;
input clock1;
input clock2;
input clock3;
// clock enable ports
input ena0;
input ena1;
input ena2;
input ena3;
// clear ports
input aclr0;
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -