// megafunction wizard: %8B10B Encoder/Decoder v1.4.0%

// ============================================================
// Megafunction Name(s):
// 			ENC_aot1151_enc8b10b
// ============================================================
// Generated by ed8b10b 1.4.0 [Altera, IP Toolbench v1.2.3 build12]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2004 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera.  Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner.  Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors.  No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.


module ENC (
	clk,
	reset_n,
	idle_ins,
	kin,
	ena,
	datain,
	rdin,
	rdforce,
	kerr,
	dataout,
	valid,
	rdout,
	rdcascade);

	parameter QTB = "on";
	parameter QTB_p_cbx_hdl_language = "verilog";
	parameter QTB_p_dual = "0";
	parameter QTB_p_product = "8b10b";
	parameter QTB_p_comma_only = "0";
	parameter QTB_p_flow_ctrl = "0";
	parameter QTB_p_keep_first_idle = "0";
	parameter QTB_p_channels = "1";
	parameter QTB_p_bytelanes = "16";
	parameter QTB_p_lut_implement = "gates";
	parameter QTB_p_broadcast = "0";
	parameter QTB_p_rx_pll_locked = "0";
	parameter QTB_p_enable_rx_rec_clk = "0";
	parameter QTB_p_enable_rx_locklost = "0";
	parameter QTB_p_iptb_top = "ENC";
	parameter QTB_p_modulename = "ed8b10b";
	parameter QTB_p_direction = "encoder";
	parameter QTB_p_target = "t_rtl_enc";
	parameter QTB_p_portlist = "t_pl_enc";
	parameter QTB_p_family = "CYCLONE";
	parameter QTB_devicefamily = "Cyclone";
	parameter QTB_plugin_task_visible = "1";
	parameter QTB_language = "Verilog HDL";
	parameter QTB_enabled = "1";

	input		clk;
	input		reset_n;
	input		idle_ins;
	input		kin;
	input		ena;
	input	[7:0]	datain;
	input		rdin;
	input		rdforce;
	output		kerr;
	output	[9:0]	dataout;
	output		valid;
	output		rdout;
	output		rdcascade;


	ENC_aot1151_enc8b10b	ENC_aot1151_enc8b10b_inst(
		.clk(clk),
		.reset_n(reset_n),
		.idle_ins(idle_ins),
		.kin(kin),
		.ena(ena),
		.datain(datain),
		.rdin(rdin),
		.rdforce(rdforce),
		.kerr(kerr),
		.dataout(dataout),
		.valid(valid),
		.rdout(rdout),
		.rdcascade(rdcascade));
endmodule

// =========================================================
// ed8b10b Wizard Data
// ===============================
// DO NOT EDIT FOLLOWING DATA
// @Altera, IP Toolbench@
// Warning: If you modify this section, ed8b10b Wizard may not be able to reproduce your chosen configuration.
// 
// Retrieval info: <?xml version="1.0"?>
// Retrieval info: <MEGACORE title="8B10B Encoder/Decoder"  version="1.4.0"  iptb_version="v1.2.3 build12"  format_version="120" >
// Retrieval info:  <NETLIST_SECTION active_core="ENC_aot1151_enc8b10b" >
// Retrieval info:   <STATIC_SECTION>
// Retrieval info:    <PRIVATES>
// Retrieval info:     <NAMESPACE name = "parameterization">
// Retrieval info:      <PRIVATE name = "p_cbx_hdl_language" value="verilog"  type="STRING"  enable="1" />
// Retrieval info:      <PRIVATE name = "p_dual" value="0"  type="STRING"  enable="1" />
// Retrieval info:      <PRIVATE name = "p_product" value="8b10b"  type="STRING"  enable="1" />
// Retrieval info:      <PRIVATE name = "p_comma_only" value="0"  type="STRING"  enable="1" />
// Retrieval info:      <PRIVATE name = "p_flow_ctrl" value="0"  type="STRING"  enable="1" />
// Retrieval info:      <PRIVATE name = "p_keep_first_idle" value="0"  type="STRING"  enable="1" />
// Retrieval info:      <PRIVATE name = "p_channels" value="1"  type="STRING"  enable="1" />
// Retrieval info:      <PRIVATE name = "p_bytelanes" value="16"  type="STRING"  enable="1" />
// Retrieval info:      <PRIVATE name = "p_lut_implement" value="gates"  type="STRING"  enable="1" />
// Retrieval info:      <PRIVATE name = "p_broadcast" value="0"  type="STRING"  enable="1" />
// Retrieval info:      <PRIVATE name = "p_rx_pll_locked" value="0"  type="STRING"  enable="1" />
// Retrieval info:      <PRIVATE name = "p_enable_rx_rec_clk" value="0"  type="STRING"  enable="1" />
// Retrieval info:      <PRIVATE name = "p_enable_rx_locklost" value="0"  type="STRING"  enable="1" />
// Retrieval info:      <PRIVATE name = "p_iptb_top" value="ENC"  type="STRING"  enable="1" />
// Retrieval info:      <PRIVATE name = "p_modulename" value="ed8b10b"  type="STRING"  enable="1" />
// Retrieval info:      <PRIVATE name = "p_direction" value="encoder"  type="STRING"  enable="1" />
// Retrieval info:      <PRIVATE name = "p_target" value="t_rtl_enc"  type="STRING"  enable="1" />
// Retrieval info:      <PRIVATE name = "p_portlist" value="t_pl_enc"  type="STRING"  enable="1" />
// Retrieval info:      <PRIVATE name = "p_family" value="CYCLONE"  type="STRING"  enable="1" />
// Retrieval info:      <PRIVATE name = "devicefamily" value="Cyclone"  type="STRING"  enable="1" />
// Retrieval info:     </NAMESPACE>
// Retrieval info:     <NAMESPACE name = "simgen_enable">
// Retrieval info:      <PRIVATE name = "language" value="Verilog HDL"  type="STRING"  enable="1" />
// Retrieval info:      <PRIVATE name = "enabled" value="1"  type="BOOLEAN"  enable="1" />
// Retrieval info:     </NAMESPACE>
// Retrieval info:     <NAMESPACE name = "serializer"/>
// Retrieval info:    </PRIVATES>
// Retrieval info:    <FILES/>
// Retrieval info:    <PORTS>
// Retrieval info:     <PORT name = "clk" direction="INPUT"  connect_to="clk"  default="NODEFVAL"  width="1"  description="" />
// Retrieval info:     <PORT name = "reset_n" direction="INPUT"  connect_to="reset_n"  default="NODEFVAL"  width="1"  description="" />
// Retrieval info:     <PORT name = "idle_ins" direction="INPUT"  connect_to="idle_ins"  default="NODEFVAL"  width="1"  description="" />
// Retrieval info:     <PORT name = "kin" direction="INPUT"  connect_to="kin"  default="NODEFVAL"  width="1"  description="" />
// Retrieval info:     <PORT name = "ena" direction="INPUT"  connect_to="ena"  default="NODEFVAL"  width="1"  description="" />
// Retrieval info:     <PORT name = "datain" direction="INPUT"  connect_to="datain"  default="NODEFVAL"  width="8"  description="" />
// Retrieval info:     <PORT name = "kerr" direction="OUTPUT"  connect_to="kerr"  default="NODEFVAL"  width="1"  description="" />
// Retrieval info:     <PORT name = "dataout" direction="OUTPUT"  connect_to="dataout"  default="NODEFVAL"  width="10"  description="" />
// Retrieval info:     <PORT name = "valid" direction="OUTPUT"  connect_to="valid"  default="NODEFVAL"  width="1"  description="" />
// Retrieval info:     <PORT name = "rdin" direction="INPUT"  connect_to="rdin"  default="NODEFVAL"  width="1"  description="" />
// Retrieval info:     <PORT name = "rdforce" direction="INPUT"  connect_to="rdforce"  default="NODEFVAL"  width="1"  description="" />
// Retrieval info:     <PORT name = "rdout" direction="OUTPUT"  connect_to="rdout"  default="NODEFVAL"  width="1"  description="" />
// Retrieval info:     <PORT name = "rdcascade" direction="OUTPUT"  connect_to="rdcascade"  default="NODEFVAL"  width="1"  description="" />
// Retrieval info:    </PORTS>
// Retrieval info:    <LIBRARIES/>
// Retrieval info:   </STATIC_SECTION>
// Retrieval info:  </NETLIST_SECTION>
// Retrieval info: </MEGACORE>
// =========================================================