#ifndef _AT91_PIO_DEFINE_HEADER#define _AT91_PIO_DEFINE_HEADER/*---------------------------PIOC-------------------*/#define PIOA_BASE_ADDR	(0xFFFFF400)#define PIOB_BASE_ADDR	(0xFFFFF600)#define	PIOC_BASE_ADDR	(0xFFFFF800)#define PIOD_BASE_ADDR	(0xFFFFFA00)#define	PIO_PDR_OFFSET	(0x04)#define	PIO_ASR_OFFSET	(0x70)#define	PIO_BSR_OFFSET	(0x74)#define	PIOC_ENABLE_D16	(0xFFFF0000)#ifndef _ASMLANGUAGEtypedef struct _AT91_PIO_S{	AT91_REG	 PIO_PER; 	/* PIO Enable Register			*/	AT91_REG	 PIO_PDR; 	/* PIO Disable Register                 */	AT91_REG	 PIO_PSR; 	/* PIO Status Register                  */	AT91_REG	 Resv0[1]; 	/*                                      */	AT91_REG	 PIO_OER; 	/* Output Enable Register               */	AT91_REG	 PIO_ODR; 	/* Output Disable Registerr             */	AT91_REG	 PIO_OSR; 	/* Output Status Register               */	AT91_REG	 Resv1[1]; 	/*                                      */	AT91_REG	 PIO_IFER; 	/* Input Filter Enable Register         */	AT91_REG	 PIO_IFDR; 	/* Input Filter Disable Register        */	AT91_REG	 PIO_IFSR; 	/* Input Filter Status Register         */	AT91_REG	 Resv2[1]; 	/*                                      */	AT91_REG	 PIO_SODR; 	/* Set Output Data Register             */	AT91_REG	 PIO_CODR; 	/* Clear Output Data Register           */	AT91_REG	 PIO_ODSR; 	/* Output Data Status Register          */	AT91_REG	 PIO_PDSR; 	/* Pin Data Status Register             */	AT91_REG	 PIO_IER; 	/* Interrupt Enable Register            */	AT91_REG	 PIO_IDR; 	/* Interrupt Disable Register           */	AT91_REG	 PIO_IMR; 	/* Interrupt Mask Register              */	AT91_REG	 PIO_ISR; 	/* Interrupt Status Register            */	AT91_REG	 PIO_MDER; 	/* Multi-driver Enable Register         */	AT91_REG	 PIO_MDDR; 	/* Multi-driver Disable Register        */	AT91_REG	 PIO_MDSR; 	/* Multi-driver Status Register         */	AT91_REG	 Resv3[1]; 	/*                                      */	AT91_REG	 PIO_PPUDR; 	/* Pull-up Disable Register             */	AT91_REG	 PIO_PPUER; 	/* Pull-up Enable Register              */	AT91_REG	 PIO_PPUSR; 	/* Pad Pull-up Status Register          */	AT91_REG	 Resv4[1]; 	/*                                      */	AT91_REG	 PIO_ASR; 	/* Select A Register                    */	AT91_REG	 PIO_BSR; 	/* Select B Register                    */	AT91_REG	 PIO_ABSR; 	/* AB Select Status Register            */	AT91_REG	 Resv5[9]; 	/*                                      */	AT91_REG	 PIO_OWER; 	/* Output Write Enable Register         */	AT91_REG	 PIO_OWDR; 	/* Output Write Disable Register        */	AT91_REG	 PIO_OWSR; 	/* Output Write Status Register         */	AT91_REG	 Resv6[85]; 	/*                                      */}AT91_PIO_S;                             #endif/* PIOA config:PA0:	clock output 3	/BPA1:	clock output 0	/BPA2:	IRQ4			/BPA3:	IRQ5			/BPA4:	clock output 1	/BPA5:	txd3			/BPA6:	rxd3			/BPA7:	ETXCK			/APA8:	eth enable		/APA9:	eth tx0			/APA10:	eth tx1			/APA11:	eth ECRS		/APA12:	eth rx0			/APA13:	eth rx1			/APA14:	eth ERXER		/APA15:	eth EMDC		/APA16:	eth EMDIO		/APA17:	TXD0			/APA18:	RXD0			/APA19:	UART SCK0		/APA20:	UART CTS0		/APA21:	UART RTS0		/APA22:	UART RXD2		/APA23:	UART TXD2		/APA24:	UART SCK2		/APA25:	TWD				/APA26:	TWCK			/APA27:	TCLK3			/BPA28:	TCLK4			/BPA29:	TCLK5			/BPA30:	DRXD			/APA31:	DTXD			/A   */#define AT91_PIOA_ASR_VALUE	 0xC7FFFF80#define AT91_PIOA_BSR_VALUE	 0x3800007F#define AT91_PIOA_OER_VALUE	 (0&(~(AT91_PIOA_ASR_VALUE|AT91_PIOA_BSR_VALUE)))#define AT91_PIOA_ODR_VALUE	 (~(AT91_PIOA_OER_VALUE)&(~(AT91_PIOA_ASR_VALUE|AT91_PIOA_BSR_VALUE)))/* PIOA config:PB0:	RTS3			/BPB1:	CTS3			/BPB2:	SCK3			/BPB3:	MCDA1			/BPB4:	MCDA2			/BPB5:	MCDA3			/BPB6:	TIOA3			/BPB7:	TIOB3			/BPB8:	TIOA4			/BPB9:	TIOB4			/BPB10:	TIOA5			/BPB11:	TIOB5			/BPB12:	ETX2			/BPB13:	ETX3			/BPB14:	ETXER			/BPB15:	ERX2			/BPB16:	ERX3			/BPB17:	ERXDV			/BPB18:	ECOL			/BPB19:	EXRXCK			/BPB20:	UART TXD1		/APB21:	UART RXD1		/APB22:	UART SCK1		/APB23:	UART DCD1		/APB24:	UART CTS1		/APB25:	DSR1			/APB26:	RTS1			/APB27:	PCK0			/APB28:	FIQ				/APB29:	IRQ0			/APB30:	DUMMY			/0PB31:	DUMMY			/0   */#define AT91_PIOB_ASR_VALUE	 0x3FF00000#define AT91_PIOB_BSR_VALUE	 0x000FFFFF#define AT91_PIOB_OER_VALUE	 (0&(~(AT91_PIOB_ASR_VALUE|AT91_PIOB_BSR_VALUE)))#define AT91_PIOB_ODR_VALUE	 (~(AT91_PIOB_OER_VALUE)&(~(AT91_PIOB_ASR_VALUE|AT91_PIOB_BSR_VALUE)))  /* PIOC config:                           PC0:	IO			/0        PC1:	IO			/0        PC2:	IO			/0        PC3:	IO			/0        PC4:	IO			/0        PC5:	IO			/0        PC6:	IO			/0        PC7:	A23			/A                                                  PC8:	A24			/A        PC9:	A24			/A        PC10:	NCS4		/A        PC11:	NCS5		/A        PC12:	NCS6		/A        PC13:	NCS7		/A        PC14:	IO			/0        PC15:	IO			/0                                                  PC16:	D16			/A        PC17:	D17			/A        PC18:	 			/A        PC19:	 			/A        PC20:	   			/A        PC21:	   			/A        PC22:	   			/A        PC23:	   			/A        PC24:	   			/A                                                  PC25:	 			/A        PC26:	 			/A        PC27:	 			/A        PC28:	 			/APC29:	 			/A                                                  PC30:	 			/A        PC31:	 			/A                                                   */                                       #define AT91_PIOC_ASR_VALUE	 0xFFFF3F80#define AT91_PIOC_BSR_VALUE	 0x00000000#define AT91_PIOC_OER_VALUE	 (0&(~(AT91_PIOC_ASR_VALUE|AT91_PIOC_BSR_VALUE)))#define AT91_PIOC_ODR_VALUE	 (~(AT91_PIOC_OER_VALUE)&(~(AT91_PIOC_ASR_VALUE|AT91_PIOC_BSR_VALUE)))/* PIOD config:                   PD0:	IO			/0PD1:	IO			/0PD2:	IO			/0PD3:	IO			/0PD4:	IO			/0PD5:	IO			/0PD6:	IO			/0PD7:	IO			/0                                  PD8:	IO			/0PD9:	IO			/0PD10:	IO			/0        PD11:	IO			/0        PD12:	IO			/0        PD13:	IO			/0        PD14:	IO			/0PD15:	IO			/0                                  PD16:	IO			/0PD17:	IO			/0PD18:	IO 			/0PD19:	IO 			/0PD21:	IO   		/0PD22:	IO   		/0PD24:	IO   		/0                                  PD25:	IO 			/0PD26:	IO 			/0PD27:	IO 			/0PD28:	IO 			/0PD29:	IO 			/0                                  PD30:	IO 			/0PD31:	IO 			/0                                   */   #define AT91_PIOD_ASR_VALUE	 0x00000000#define AT91_PIOD_BSR_VALUE	 0x00000000#define AT91_PIOD_OER_VALUE	 (0&(~(AT91_PIOD_ASR_VALUE|AT91_PIOD_BSR_VALUE)))#define AT91_PIOD_ODR_VALUE	 (~(AT91_PIOD_OER_VALUE)&(~(AT91_PIOD_ASR_VALUE|AT91_PIOD_BSR_VALUE)))#endif	/*_AT91_PIO_DEFINE_HEADER*/