switch( rtl8305port)     {    	case 0:	regval&= ~(RTL_PVID_BIT_WITH <<RTL_PORT0_PVID_BIT_SHL);			regval&=pvid<<RTL_PORT0_PVID_BIT_SHL;				break;	case 1: 	regval&= ~(RTL_PVID_BIT_WITH <<RTL_PORT1_PVID_BIT_SHL);			regval&=pvid<<RTL_PORT1_PVID_BIT_SHL;				break;	case 2:	regval&= ~(RTL_PVID_BIT_WITH <<RTL_PORT2_PVID_BIT_SHL);			regval&=pvid<<RTL_PORT2_PVID_BIT_SHL;				break;	case 3:	regval&= ~(RTL_PVID_BIT_WITH <<RTL_PORT3_PVID_BIT_SHL);			regval&=pvid<<RTL_PORT3_PVID_BIT_SHL;				break;	case 4:	regval&= ~(RTL_PVID_BIT_WITH <<RTL_PORT4_PVID_BIT_SHL);			regval&=pvid<<RTL_PORT4_PVID_BIT_SHL;				break;	default:			return ERR_PORT_ERROR;    }       realtekMiiWriteRtn(port,phyAddr, vlanReg, regval);    return realtekSoftReset(port);}/************************************************************ * * Configure the rtl8305  vlan table  *  */IxEthAccStatusrealtekVlanSetup(UINT32 port, UINT16 vid, UINT8 portBitmap){    UINT16 regval=0;        UINT8 phyAddr=0;    UINT8 vlanReg =0;	    if(port!=PORTB)  return ERR_PORT_ERROR;    if(vid >= 5) return ERR_VID_ERROR;    phyAddr = RTL_VLAN_MEMBER_REGISTER[vid].PHY_address;    vlanReg = RTL_VLAN_MEMBER_REGISTER[vid].VLAN_register;    realtekMiiReadRtn(port, phyAddr,vlanReg, &regval);    realtekMiiReadRtn(port, phyAddr,vlanReg, &regval);    portBitmap &= RTL_VLAN_MEMBER_BIT_WITH;    switch(vid)     {    	case VLANA:  regval &=~(RTL_VLAN_MEMBER_BIT_WITH <<RTL_VLANA_MEMBER_BIT_SHL);		       	regval &= portBitmap <<RTL_VLANA_MEMBER_BIT_SHL;				break;	case VLANB:	regval &=~(RTL_VLAN_MEMBER_BIT_WITH <<RTL_VLANB_MEMBER_BIT_SHL);		       	regval &= portBitmap <<RTL_VLANB_MEMBER_BIT_SHL;				break;	case VLANC:	regval &=~(RTL_VLAN_MEMBER_BIT_WITH <<RTL_VLANC_MEMBER_BIT_SHL);		       	regval &= portBitmap <<RTL_VLANC_MEMBER_BIT_SHL; 				break;	case VLAND:	regval &=~(RTL_VLAN_MEMBER_BIT_WITH <<RTL_VLAND_MEMBER_BIT_SHL);		       	regval &= portBitmap <<RTL_VLAND_MEMBER_BIT_SHL;				break;	case VLANE:	regval &=~(RTL_VLAN_MEMBER_BIT_WITH <<RTL_VLANE_MEMBER_BIT_SHL);		       	regval &= portBitmap <<RTL_VLANE_MEMBER_BIT_SHL;				break;	default:			return ERR_VID_ERROR;     }	    realtekMiiWriteRtn(port,phyAddr, vlanReg, regval);    return realtekSoftReset(port);}/************************************************************ * * Configure the rtl8305  vlan disable or enable  *  */IxEthAccStatusrealtekVlanCtrl(UINT32 port,BOOL VLANEnable){    UINT16 regval=0;        UINT8 phyAddr=0;    UINT8 vlanReg =0;    if(port!=PORTB)  return ERR_PORT_ERROR;    phyAddr = RTL_VLAN_CTRL_REGISTER.PHY_address;    vlanReg = RTL_VLAN_CTRL_REGISTER.VLAN_register;    realtekMiiReadRtn(port, phyAddr,vlanReg, &regval);    realtekMiiReadRtn(port, phyAddr,vlanReg, &regval);    if(VLANEnable)     {	regval &=~(RTL_VLAN_CTRL_DisableVLAN_BIT|RTL_VLAN_CTRL_DISTagAware_BIT|RTL_VLAN_CTRL_DISMemFilter_BIT);    }    else   {	regval = 0xffff;   }	    realtekMiiWriteRtn(port,phyAddr, vlanReg, regval);    return realtekSoftReset(port);}/************************************************************ * * Configure the rtl8305  priority disable or enable  *  */IxEthAccStatusrealtekPriorityCtrl(UINT32 port,UINT16 CtrlBit,BOOL PriorityEnable){    UINT16 regval=0;        UINT8 phyAddr=0;    UINT8 Reg =0;    if(port!=PORTB)  return ERR_PORT_ERROR;    phyAddr = RTL_PRIORITY_CTRL_REGISTER.PHY_address;    Reg = RTL_PRIORITY_CTRL_REGISTER.VLAN_register;    realtekMiiReadRtn(port, phyAddr,Reg, &regval);    realtekMiiReadRtn(port, phyAddr,Reg, &regval);	    if(PriorityEnable)     {	regval &=~CtrlBit;    }    else   {	regval |= CtrlBit;   }	    realtekMiiWriteRtn(port,phyAddr, Reg, regval);    return realtekSoftReset(port);}/************************************************************ * * issue  the rtl8305  software reset  command *  */IxEthAccStatusrealtekSoftReset(UINT32 port){    UINT16 regval=0;        UINT8 phyAddr=0;    UINT8 Reg =0;    if(port!=PORTB)  return ERR_PORT_ERROR;    phyAddr = RTL_PORT_CTRL_REGISTER.PHY_address;    Reg = RTL_PORT_CTRL_REGISTER.VLAN_register;    realtekMiiReadRtn(port, phyAddr,Reg, &regval);    realtekMiiReadRtn(port, phyAddr,Reg, &regval);    regval |=RTL_PORT_CTRL_SOFTRESET_BIT;	    return realtekMiiWriteRtn(port,phyAddr, Reg, regval);}/***************************************************************** * *  Link state query functions */IxEthAccStatusrealtekMiiLinkStatus(UINT32 port,UINT32 phyAddr, 		      BOOL *linkUp,		      BOOL *speed100, 		      BOOL *fullDuplex,		      BOOL *autoneg){    UINT16 regval;    /*Need to read the register twice here to flush PHY*/    realtekMiiReadRtn(port,phyAddr,  IX_ETH_ACC_MII_STAT_REG, &regval);    realtekMiiReadRtn(port,phyAddr,  IX_ETH_ACC_MII_STAT_REG, &regval);    if((regval & IX_ETH_ACC_MII_SR_LINK_STATUS) != 0)    {	*linkUp = TRUE;    }    else    {	*linkUp = FALSE;    }    if((regval & IX_ETH_ACC_MII_SR_TX_FULL_DPX) != 0)    {	*speed100 = TRUE;	*fullDuplex = TRUE;    }    if((regval & IX_ETH_ACC_MII_SR_TX_HALF_DPX) != 0)    {	*speed100 = TRUE;	*fullDuplex = FALSE;    }    if((regval & IX_ETH_ACC_MII_SR_10T_FULL_DPX) != 0)    {	*speed100 = FALSE;	*fullDuplex = TRUE;    }    if((regval & IX_ETH_ACC_MII_SR_10T_HALF_DPX) != 0)    {	*speed100 = FALSE;	*fullDuplex = FALSE;    }	    if(((regval & IX_ETH_ACC_MII_SR_AUTO_NEG) != 0)		&& ((regval & IX_ETH_ACC_MII_SR_AUTO_SEL)!=0))    {	*autoneg = TRUE;    }    else    {	*autoneg = FALSE;    }        return IX_ETH_ACC_SUCCESS;   }IxEthAccStatusrealtekMiiShow (UINT32 port,UINT32 phyAddr){    UINT16 regval;    /*Need to read the register twice here to flush PHY*/    if(realtekMiiReadRtn(port, phyAddr,  IX_ETH_ACC_MII_STAT_REG, &regval)        != IX_ETH_ACC_SUCCESS)    {	return IX_ETH_ACC_FAIL;    }   realtekMiiReadRtn(port,phyAddr,  IX_ETH_ACC_MII_STAT_REG, &regval);    printf("PHY Status: \n");    if((regval & IX_ETH_ACC_MII_SR_LINK_STATUS) != 0)    {	printf("    Link is Up\n");    }    else    {	printf("    Link is Down\n");    }    if((regval & IX_ETH_ACC_MII_SR_REMOTE_FAULT) != 0)    {	printf("    Remote fault detected\n");    }  if((regval & IX_ETH_ACC_MII_SR_TX_FULL_DPX) != 0)    {	printf("    Speed: 100Mb/s\n");	printf("    Full Duplex\n");    }    if((regval & IX_ETH_ACC_MII_SR_TX_HALF_DPX) != 0)    {	printf("    Speed: 100Mb/s\n");	printf("    Half Duplex\n");    }    if((regval & IX_ETH_ACC_MII_SR_10T_FULL_DPX) != 0)    {	printf("    Speed: 10Mb/s\n");	printf("    Full Duplex\n");    }    if((regval & IX_ETH_ACC_MII_SR_10T_HALF_DPX) != 0)    {	printf("    Speed: 10Mb/s\n");	printf("    Half Duplex\n");    }        if((regval & IX_ETH_ACC_MII_SR_AUTO_SEL)!=0)    {	printf("    Auto Negotiation Enabled\n");    }    else    {	printf("    Auto Negotiation Disabled\n");    }    if((regval & IX_ETH_ACC_MII_SR_AUTO_NEG) != 0)    {	printf("    Auto Negotiation Completed\n");    }    else    {	printf("    Auto Negotiation Not Completed\n");    }    return IX_ETH_ACC_SUCCESS;}IxEthAccStatusrealtekMiiStatsShow (UINT32 port,UINT32 phyAddr){    UINT16 regval;	    printf("Regisers on PHY at address 0x%x\n", phyAddr);    realtekMiiReadRtn(port,phyAddr, IX_ETH_ACC_MII_CTRL_REG, &regval);    realtekMiiReadRtn(port,phyAddr, IX_ETH_ACC_MII_CTRL_REG, &regval);    printf("    Control Register                  :      0x%x\n", regval);    realtekMiiReadRtn(port,phyAddr,  IX_ETH_ACC_MII_STAT_REG, &regval);    printf("    Status Register                   :      0x%x\n", regval);       realtekMiiReadRtn(port,phyAddr,  IX_ETH_ACC_MII_AN_ADS_REG, &regval);    printf("    Auto Neg ADS Register             :      0x%x\n", regval);    realtekMiiReadRtn(port,phyAddr,  IX_ETH_ACC_MII_AN_PRTN_REG, &regval);    printf("    Auto Neg Partner Ability Register :      0x%x\n", regval);    realtekMiiReadRtn(port,phyAddr,  IX_ETH_ACC_MII_AN_EXP_REG, &regval);    printf("    Auto Neg Expansion Register       :      0x%x\n", regval);    realtekMiiReadRtn(port,phyAddr,  IX_ETH_ACC_MII_STAT_REG, &regval);        printf("This local PHY's Capabilities:\n");    if((regval & IX_ETH_ACC_MII_SR_AUTO_SEL) != 0)    {	printf("    Auto Speed Select capable PHY\n");    }    else    {	printf("    Non Auto Speed Select capable PHY\n");    }    if((regval & IX_ETH_ACC_MII_SR_10T_HALF_DPX) != 0)    {	printf("    10T Half Duplex Capable PHY\n");    }    else    {	printf("    Non 10T Half Duplex Capable PHY\n");    }    if((regval & IX_ETH_ACC_MII_SR_10T_FULL_DPX) != 0)    {	printf("    10T Full Duplex Capable PHY\n");    }    else    {	printf("    Non 10T Full Duplex Capable PHY\n");    }    if((regval & IX_ETH_ACC_MII_SR_TX_HALF_DPX) != 0)    {	printf("    100Tx HD capable\n");    }    else    {	printf("    Non 100TX HD capable\n");    }    if((regval & IX_ETH_ACC_MII_SR_TX_FULL_DPX) != 0)    {	printf("    100TX FD capable\n");    }    else    {	printf("     Non 100TX FD capable\n");    }    if((regval & IX_ETH_ACC_MII_SR_T4) != 0)    {	printf("    T4 capable\n");    }    printf("PHY Status: \n");    if((regval & IX_ETH_ACC_MII_SR_LINK_STATUS) != 0)    {	printf("    Link is Up\n");    }    else    {	printf("    Link is Down\n");    }    if((regval & IX_ETH_ACC_MII_SR_REMOTE_FAULT) != 0)    {	printf("    Remote fault detected\n");    }    else    {	printf("    No Remote fault detected\n");    }    if((regval & IX_ETH_ACC_MII_SR_AUTO_NEG) != 0)    {	printf("    Auto Negotiation Completed\n");    }    else    {	printf("    Auto Negotiation Not Completed\n");    }    return IX_ETH_ACC_SUCCESS;}IxEthAccStatusrealtekMdioShow (UINT32 port){    UINT32 regval;    realtekMdioCmdRead(port,&regval);        printf("MDIO command register\n");    printf("    Go bit      : 0x%x\n", (regval & BIT(31)) >> 31);    printf("    MDIO Write  : 0x%x\n", (regval & BIT(26)) >> 26);    printf("    PHY address : 0x%x\n", (regval >> 21) & 0x1f);    printf("    Reg address : 0x%x\n", (regval >> 16) & 0x1f);	    realtekMdioStatusRead(port,&regval);    printf("MDIO status register\n");    printf("    Read OK     : 0x%x\n", (regval & BIT(31)) >> 31);    printf("    Read Data   : 0x%x\n", (regval >> 16) & 0xff);    return IX_ETH_ACC_SUCCESS;   }