/* wrSbc8260Atm.h - board header *//* Copyright 1984-2001 Wind River Systems, Inc. *//*modification history--------------------01b,13dec01,g_h  Add the macro DEC_CLK_TO_INC01a,05may01,g_h	 adopted from sbc8260/sbc8260.h (ver 01b)*/#ifndef	__INCwrSbc8260Atmh#define	__INCwrSbc8260Atmh#ifdef __cplusplusextern "C" {#endif/* Include files */#include "drv/mem/memDev.h"#include "drv/mem/flashDev.h"#include "drv/intrCtl/m8260IntrCtl.h"#define BUS_TYPE  NONE /* board bus interface  */#define STRING_MATCH  0/* On board device I/O adress */         #define LOCAL_BUS_SDRAM_ADRS      0x10000000 /* Local Bus SDRAM base adrs */#define LOCAL_BUS_SDRAM_SIZE      0x01000000 /* 16MB Local Bus SDRAM */#define LOCAL_ATM_SUNI_DUAL_ADDR  0x12000000 /* ATM dual phy base address */#define LOCAL_ATM_SUNI_DUAL_SIZE  0x00100000 /* ATM dual phy size */#define EEPROM_ADRS               0x22020000 /* EEPROM base address */#define EEPROM_SIZE               0x2000     /* 8KB EEPROM */#define INTERNAL_MEM_MAP_ADDR     0xF0000000 /* Internal Memory Map base Address  */#define INTERNAL_MEM_MAP_SIZE     0x00020000 /* 128 K bytes      */#define BSCR_BASE_ADRS            0x21000000 /* Board Control and Status reg base address */#define BSCR_LED_REGISTER         *((UINT8 *)(BSCR_BASE_ADRS+1)) /* Write Only */#define BSCR_USER_SWITCH          *((UINT8 *)(BSCR_BASE_ADRS+1)) /* Read Only */#define BSCR_PRESENT_DETECT       *((UINT8 *)(BSCR_BASE_ADRS))   /* Read Only *//* Reset Configuration Locations */#define HRDW_CONFIG_BYTE1         0xfe000000 /* Most Significant Byte */#define HRDW_CONFIG_BYTE2         0xfe000008         #define HRDW_CONFIG_BYTE3         0xfe000010        #define HRDW_CONFIG_BYTE4         0xfe000018/* Dynamically determine system clock rate */#define  PPC_TMR_RATE_SET_ADJUST  (void)sysClkRateAdjust(&sysDecClkFrequency)#define  DEC_ADJUSTMENT           4#define  DEC_CLK_TO_INC	          DEC_ADJUSTMENT    /* Cache Commands  */#define CACHE_DISABLE_CMD         0x0400     #define CACHE_ENABLE              0x0200     #define CACHE_UNLOCK_ALL          0x0A00#define CACHE_INVALIDATE_ALL      0x0C00#define IMMR_ISB_MASK		  0xFFFE0000 /* Internal Space Base mask */#define IMMR_PARTNUM_MASK	  0x0000FF00 /* Part Number mask */#define IMMR_MASKNUM_MASK	  0x000000FF /* Mask Number mask */#define PARTNUM_MASK              0x0000FF00 /* part number file in IMMR */#define MASKNUM_MASK              0x000000FF#define MODCK_H_MASK              0x0F#define SILICON_REV_PREA1         0x00#define SILICON_REV_A1            0x11/* Define Clock Speed and source  */#define  FREQ_33MHZ               33000000#define  FREQ_66MHZ               66000000#define  FREQ_100MHZ              100000000#define  FREQ_133MHZ              133000000#define  FREQ_150MHZ              150000000#define  FREQ_166MHZ              166000000#define  FREQ_200MHZ              200000000#define  FREQ_233MHZ              233000000#define  FREQ_266MHZ              266000000#define  FREQ_300MHZ              300000000/* Clock Parameters */#define	SYS_CLK_RATE_MIN          1    /* min system clock rate    */#define	SYS_CLK_RATE_MAX          8000 /* max system clock rate    */#define	AUX_CLK_RATE_MIN          1    /* min auxiliary clock rate */#define	AUX_CLK_RATE_MAX          8000 /* max auxiliary clock rate *//* Define CPU type and number of Serial channels  */#define BUS                       0      /* bus-less board            */#define CPU                       PPC603 /* CPU type                  */#define N_SIO_CHANNELS            2      /* No. serial I/O channels   *//* create a single macro INCLUDE_MMU */#if defined(INCLUDE_MMU_BASIC) || defined(INCLUDE_MMU_FULL)#define INCLUDE_MMU#endif/* Only one can be selected, FULL overrides BASIC */#ifdef INCLUDE_MMU_FULL#   undef INCLUDE_MMU_BASIC#endif/* SIU Group */#define INIT_IMMR       0x01A8#define INIT_SIUMCR     0x0000#define INIT_SYPCR      0x0004#define INIT_SWT        0x0008#define INIT_SWSR       0x000E#define INIT_BCR        0x0024#define INIT_PPC_ACR    0x0028#define INIT_PPC_ALRH   0x002C#define INIT_PPC_ALRL   0x0030#define INIT_LCL_ACR    0x0034#define INIT_LCL_ALRH   0x0038#define INIT_LCL_ALRL   0x003C#define INIT_TESCR1     0x0040#define INIT_TESCR2     0x0044#define INIT_LTESCR1    0x0048#define INIT_LTESCR2    0x004C#define INIT_PDTEA      0x0050#define INIT_PDTEM      0x0054#define INIT_LDTEA      0x0058#define INIT_LDTEM      0x005C/* MEMC Group */#define INIT_MAR        0x0168#define INIT_MAMR       0x0170#define INIT_MBMR       0x0174#define INIT_MCMR       0x0178#define INIT_MPTPR      0x0184#define INIT_MDR        0x0188#define INIT_PSDMR      0x0190#define INIT_LSDMR      0x0194#define INIT_PURT       0x0198#define INIT_PSRT       0x019C#define INIT_LURT       0x01A0#define INIT_LSRT       0x01A4#define INIT_PCIBR0     0x01AC#define INIT_PCIBR1     0x01B0#define INIT_PCIMSK0    0x01C4#define INIT_PCIMSK1    0x01C8#define INIT_RMR        0x0C94 /* Clock Group */#define INIT_SCCR       0x0c80/* Chip Select Group */#define INIT_OR0        0x0104#define INIT_BR0        0x0100#define INIT_OR1        0x010C#define INIT_BR1        0x0108#define INIT_OR2        0x0114#define INIT_BR2        0x0110#define INIT_OR3        0x011C#define INIT_BR3        0x0118#define INIT_OR4        0x0124#define INIT_BR4        0x0120#define INIT_OR5        0x012C#define INIT_BR5        0x0128#define INIT_OR6        0x0134#define INIT_BR6        0x0130#define INIT_OR7        0x013C#define INIT_BR7        0x0138#define INIT_OR8        0x0144#define INIT_BR8        0x0140#define INIT_OR9        0x014C#define INIT_BR9        0x0148#define INIT_OR10       0x0154#define INIT_BR10       0x0150#define INIT_OR11       0x015C#define INIT_BR11       0x0158/* 60x Bus Group */#define INIT_PSDMR1    0x0190#define INIT_MEM0      0x0000#define INIT_PSDMR2    0x0190#define INIT_MEM1      0x0001#define INIT_MEM2      0x0002#define INIT_MEM3      0x0003#define INIT_MEM4      0x0004#define INIT_MEM5      0x0005#define INIT_MEM6      0x0006#define INIT_MEM7      0x0007#define INIT_MEM8      0x0008#define INIT_PSDMR3    0x0190#define INIT_MEM9      0x0009#define INIT_PSDMR4    0x0190/* Local Bus Group */#define INIT_LSDMR1    0x0194#define INIT_LSDMR2    0x0194#define INIT_LSDMR3    0x0194#define INIT_LSDMR4    0x0194/* Port A, B, C and D Defines */#define PA31    (0x00000001)#define PA30    (0x00000002)#define PA29    (0x00000004)#define PA28    (0x00000008)#define PA27    (0x00000010)#define PA26    (0x00000020)#define PA25    (0x00000040)#define PA24    (0x00000080)#define PA23    (0x00000100)#define PA22    (0x00000200)#define PA21    (0x00000400)#define PA20    (0x00000800)#define PA19    (0x00001000)#define PA18    (0x00002000)#define PA17    (0x00004000)#define PA16    (0x00008000)#define PA15    (0x00010000)#define PA14    (0x00020000)#define PA13    (0x00040000)#define PA12    (0x00080000)#define PA11    (0x00100000)#define PA10    (0x00200000)#define PA9     (0x00400000)#define PA8     (0x00800000)#define PA7     (0x01000000)#define PA6     (0x02000000)#define PA5     (0x04000000)#define PA4     (0x08000000)#define PA3     (0x10000000)#define PA2     (0x20000000)#define PA1     (0x40000000)#define PA0     (0x80000000)#define PB31    (0x00000001)#define PB30    (0x00000002)#define PB29    (0x00000004)#define PB28    (0x00000008)#define PB27    (0x00000010)#define PB26    (0x00000020)#define PB25    (0x00000040)#define PB24    (0x00000080)#define PB23    (0x00000100)#define PB22    (0x00000200)#define PB21    (0x00000400)#define PB20    (0x00000800)#define PB19    (0x00001000)#define PB18    (0x00002000)#define PB17    (0x00004000)#define PB16    (0x00008000)#define PB15    (0x00010000)#define PB14    (0x00020000)#define PB13    (0x00040000)#define PB12    (0x00080000)#define PB11    (0x00100000)#define PB10    (0x00200000)#define PB9     (0x00400000)#define PB8     (0x00800000)#define PB7     (0x01000000)#define PB6     (0x02000000)#define PB5     (0x04000000)#define PB4     (0x08000000)#define PC31    (0x00000001)#define PC30    (0x00000002)#define PC29    (0x00000004)#define PC28    (0x00000008)#define PC27    (0x00000010)#define PC26    (0x00000020)#define PC25    (0x00000040)#define PC24    (0x00000080)#define PC23    (0x00000100)#define PC22    (0x00000200)#define PC21    (0x00000400)#define PC20    (0x00000800)#define PC19    (0x00001000)#define PC18    (0x00002000)#define PC17    (0x00004000)#define PC16    (0x00008000)#define PC15    (0x00010000)#define PC14    (0x00020000)#define PC13    (0x00040000)#define PC12    (0x00080000)#define PC11    (0x00100000)#define PC10    (0x00200000)#define PC9     (0x00400000)#define PC8     (0x00800000)#define PC7     (0x01000000)#define PC6     (0x02000000)#define PC5     (0x04000000)#define PC4     (0x08000000)#define PC3     (0x10000000)#define PC2     (0x20000000)#define PC1     (0x40000000)#define PC0     (0x80000000)#define PD31    (0x00000001)#define PD30    (0x00000002)#define PD29    (0x00000004)#define PD28    (0x00000008)#define PD27    (0x00000010)#define PD26    (0x00000020)#define PD25    (0x00000040)#define PD24    (0x00000080)#define PD23    (0x00000100)#define PD22    (0x00000200)#define PD21    (0x00000400)#define PD20    (0x00000800)#define PD19    (0x00001000)#define PD18    (0x00002000)#define PD17    (0x00004000)#define PD16    (0x00008000)#define PD15    (0x00010000)#define PD14    (0x00020000)#define PD13    (0x00040000)#define PD12    (0x00080000)#define PD11    (0x00100000)#define PD10    (0x00200000)#define PD9     (0x00400000)#define PD8     (0x00800000)#define PD7     (0x01000000)#define PD6     (0x02000000)#define PD5     (0x04000000)#define PD4     (0x08000000)/* General */#ifndef TRUE#define TRUE  1#define FALSE 0#endif#undef  EIEIO#define EIEIO      WRS_ASM("	eieio")#undef  EIEIO_SYNC#define EIEIO_SYNC WRS_ASM("	eieio;	sync")#ifdef __cplusplus}#endif#endif	/* __INCwrSbc8260Atmh */