.SS "Network Configuration"SCC1 is configured as a 10Mb/s Ethernet portFCC2 is configured as a 10/100Mb/s Fast Ethernet port.SS "VME Access"NA.SS "PCI Access"NA.SS "Force Default Boot Line Option"If the FORCE_DEFAULT_BOOT_LINE is defined in "config.h", then the DEFAULT_BOOT_LINE parameters are used as boot parameters regardless of the NVRAM values previously specified. Recall, boot parameters are stored in the NVRAM device so boot parameters are not lost during a power cycle.  Defining the FORCE_DEFAULT_BOOT_LINE value is useful for debugging emulator/visionPROBE II downloaded  RAM based vxWorks images.  It is considered a DEBUG options so it should be #undef'ed for the final image.Normally the boot parameters are specified at the bootrom prompt andstored in NVRAM.  When a downloaded image executes, the boot parametersare retrieved from the NVRAM device.    This can sometimes cause undesired results.  For example, if the NVRAMhas been  previously initialized, then changing the DEFAULT_BOOT_LINEin the config.h will not result in the new settings being used. The reason being is the initialization code always takes the boot parameters from the NVRAM device. If there are sane values in the NVRAM device, theseboot parameters are used.If you intended to debug an image by downloading with WR's visionToolsand plan on changing the DEFAULT_BOOT_LINE parameters a number of times,it might be convenience to define this FORCE_DEFAULT_BOOT_LINE parameter.As a note, unitialized NVRAM device is initialized automatically withthe DEFAULT_BOOT_LINE parameters specified in the config.h file.As an alternate solution for the above scenario, the boot parameters canbe changed via the bootrom. This will store the values in NVRAM andwill subsequentially be used by the download image.  This would requirea sane bootrom and would require the target board to run via the bootromsto set the values and then halted to download the image to be debugged viathe WR Tools..SS "Using the Local Bus"If a you configures SCC or FCC use of local bus, or is building a ROM residentimage, then you MUST define INCLUDE_LOCAL_BUS_SDRAM in "config.h" as follow:FROM:.CS   #undef INCLUDE_LOCAL_BUS_SDRAM.CETO:.CS   #define INCLUDE_LOCAL_BUS_SDRAM.CE.SS "Building ROM Resident image"Before you build a rom resident vxWorks image you need to modify the following parameter in "config.h":FROM:.CS     #undef FORCE_DEFAULT_BOOT_LINE.CETO:.CS     #define FORCE_DEFAULT_BOOT_LINE.CEDon't forget to enter the correct target IP address in the DEFAULT_BOOT_LINE. For more details please read the "Force Default Boot Line Option" section.And in "config.h" to define the macro "#define INCLUDE_LOCAL_BUS_SDRAM".** With the ROM RESIDENT from the user level, Zero Copy sockets is available,    but the driver will internally and transparently convert the transmit calls    to copy sends. .SS "ROM Considerations"bootrom_uncmp.hex is provided with this BSP. The bootrom is configured to a ROM base address of 0x0. When programing the bootrom to the FLASH an offsetof 0xFFF00100 need to be given, also it's configured to use the 2 MByte On Board Flash ROM and FCC2 10/100BaseT Ethernet as default boot device and SMC1 as console device. The hard reset configuration word must be programmed separately at the flash base address of 0xFE000000 and at offsets 0x0, 0x8, 0x10, 0x18 and 0x20, see chapter 5 Reset in the MPC8260 PowerQUICC II User's Manual..SS "Switching between the FCC to SCC"The BSP is using by default the FCC channel for booting, but it also includethe SCC interface, and you can choose between them in the boot prompt. There is also an option to include the only one of the interfaces. Please follow those steps to get the BSP working only with the SCC or FCC driver instead of working with both of them:1. In "config.h" change the following lines:   FROM:.CS   #define BOOT_DEVICE SCC_FCC_END.CE   TO for Only the SCC Channel:.CS   #define BOOT_DEVICE SCC_END.CE   OR TO for Only the FCC Channels:.CS   #define BOOT_DEVICE FCC_END.CE2. In the makefile change the following lines:   FROM:.CS   MACH_EXTRA    = m8260SccEnd.obj.CETO for Only the FCC Channels:.CS   MACH_EXTRA    = #m8260SccEnd.obj.CE3. Now rebuild the bootrom and create a new VxWorks image project and build it.** Don't forget to change the device name to "motscc" in the "boot device" line    in the bootrom if you want to use the SCC channel..SS "Delivered Objects"The following images are delivered with the wrSbc8260 BSP:.IPbootrom_uncmp.IPbootrom_uncmp.hex.IPbootrom.IPbootrom.hex.IPvxWorks.IPvxWorks.st.IPm8260SccEnd.obj.LP.SS "Make Targets"Only bootrom_uncmp, bootrom, bootrom_res, vxWorks, vxWorks_romResident have been tested..SS "Dual Port RAM Map"The wrSbc8260Atm is using the m82xxDpramLib.c to allocate dynamically the necessary DPRAM memory for the serial, Ethernet and ATM channels.Key features of sysDpramLib are:    - Init the DPRAM memory with considerations of any Microcode that add been      loaded.        - Allocate aligned and non aligned memory.     - Free memory.    - Manage a special section (b000 - c000) for special FCC needs.    - Manage a special section (8000 - 9000) for special SCC needs..SS "ATM driver"You can buy from Wind River PS the ATM driver for this board. The ATM driver is The key features of ATM driver are:    - Support all of the 8260 FCC ATM features.    - Part of Tornado project facility - easy configuration.    - Integrated with the BSP.    - High performance.** NOTE: When the ATM is used the SCC channel can't be used.For more details please contact your Wind River sales representive. .SS "Interrupts".LPThe following table describes the relationship between the interruptnumber, interrupt vector, and the interrupt bit position in the SIUInterrupt Mask Register (SIMR_H and SIMR_L). Also described is themask to use to enable all interrupts of a higher priority..TS center;c c c c c s cc c c c c s cc c c c c c cnw(.3i) n n n n n l.Default				Mask to EnableInterrupt	Interrupt	Interrupt	SIMR	Higher Priority Interrupts	InterruptPriority	Number	Vector	Mask	SIMR_H	SIMR_L	Source_						HIGHEST PRIORITY1	16	0x10	H 0x00000004	0000_0000	0000_0000	TMCNT2	16	0x10	H 0x00000004	0000_0000	0000_0000	TMCNT3	17	0x11	H 0x00000002	0000_0004	0000_0000	PIT4	reserved5	19	0x13	H 0x00004000	0000_0006	0000_0000	IRQ16	27	0x20	L 0x80000000	0000_4006	0000_0000	FCC17	28	0x21	L 0x40000000	0000_4006	8000_0000	FCC28	29	0x22	L 0x20000000	0000_4006	C000_0000	FCC39	inactive10	unused11	31	0x24	L 0x08000000	0000_4006	E000_0000	MCC112	32	0x25	L 0x04000000	0000_4006	E800_0000	MCC213	inactive14	inactive15	20	0x13	H 0x00002000	0000_4006	EC00_0000	IRQ216	21	0x14	H 0x00001000	0000_6006	EC00_0000	IRQ317	22	0x15	H 0x00000800	0000_7006	EC00_0000	IRQ418	23	0x16	H 0x00000400	0000_7806	EC00_0000	IRQ519	unused20	35	0x28	L 0x00800000	0000_7C06	EC00_0000	SCC121	36	0x29	L 0x00400000	0000_7C06	EC80_0000	SCC222	37	0x2A	L 0x00200000	0000_7C06	ECC0_0000	SCC323	38	0x2B	L 0x00100000	0000_7C06	ECE0_0000	SCC424	inactive25	inactive26	inactive27	inactive28	unused29	40	0x30	H 0x00010000	0000_7C06	ECF0_0000	PC1530	12	0x0C	L 0x00000010	0001_7C06	ECF0_0000	Timer 131	41	0x31	H 0x00020000	0001_7C06	ECF0_0010	PC1432	unused33	42	0x32	H 0x00040000	0003_7C06	ECF0_0010	PC1334	10	0x0A	L 0x00000040	0007_7C06	ECF0_0010	SDMA Bus Error35	6	0x06	L 0x00000400	0007_7C06	ECF0_0050	IDMA136	unused37	43	0x33	H 0x00080000	0007_7C06	ECF0_0450	PC1238	44	0x34	H 0x00100000	000F_7C06	ECF0_0450	PC1139	7	0x07	L 0x00000200	001F_7C06	ECF0_0450	IDMA240	13	0x0D	L 0x00000008	001F_7C06	ECF0_0650	Timer 2.TE.bp.LPInterrupts, continued:.sp 3.TScenter;c c c c c s cc c c c c s cc c c c c c cnw(.3i) n n n n n l.Default				Mask to EnableInterrupt	Interrupt	Interrupt	SIMR	Higher Priority Interrupts	InterruptPriority	Number	Vector	Mask	SIMR_H	SIMR_L	Source_						HIGHEST PRIORITY41	45	0x35	H 0x00200000	001F_7C06	ECF0_0658	PC1042	unused43	unused44	3	0x03	L 0x00002000	003F_7C06	ECF0_0658	RISC Timer Table45	1	0x01	L 0x00008000	003F_7C06	ECF0_2658	I2C46	unused47	46	0x36	H 0x00400000	003F_7C06	ECF0_A658	PC948	47	0x37	H 0x00800000	007F_7C06	ECF0_A658	PC849	24	0x18	H 0x00000200	00FF_7C06	ECF0_A658	IRQ650	8	0x08	L 0x00000100	00FF_7E06	ECF0_A658	IDMA351	25	0x19	H 0x00000100	00FF_7E06	ECF0_A758	IRQ752	14	0x0E	L 0x00000004	00FF_7F06	ECF0_A758	Timer 353	unused54	unused55	48	0x38	H 0x01000000	00FF_7F06	ECF0_A75C	PC756	49	0x39	H 0x02000000	01FF_7F06	ECF0_A75C	PC657	50	0x3A	H 0x04000000	03FF_7F06	ECF0_A75C	PC558	15	0x0F	L 0x00000002	07FF_7F06	ECF0_A75C	Timer 459	unused60	51	0x3B	H 0x08000000	07FF_7F06	ECF0_A75E	PC461	unused62	9	0x09	L 0x00000080	0FFF_7F06	ECF0_A75E	IDMA463	2	0x02	L 0x00004000	0FFF_7F06	ECF0_A7DE	SPI64	52	0x3C	H 0x10000000	0FFF_7F06	ECF0_E7DE	PC365	53	0x3D	H 0x20000000	1FFF_7F06	ECF0_E7DE	PC266	4	0x04	L 0x00001000	3FFF_7F06	ECF0_E7DE	SMC167	unused68	5	0x05	L 0x00000800	3FFF_7F06	ECF0_F7DE	SMC269	54	0x3E	H 0x40000000	3FFF_7F06	ECF0_FFDE	PC170	55	0x3F	H 0x80000000	7FFF_7F06	ECF0_FFDE	PC071	unused72	unused73	reserved						LOWEST PRIORITY.TE.SH "SPECIAL CONSIDERATIONS"This section describes miscellaneous information that the user needsto know about the BSP..SS "Cache coherency between the 603 core and the CPM"The MPC8260 is not maintaining cache coherency between the 603 core and the CPM, in result of this, all the data that is transfer from the 603 to the CPM an vise versa should be placed in non-cacheable memory. For example the FCC and SCC buffers and buffer descriptors should be allocated using cacheDmaMalloc(). In this BSP the BD are located inside the CPM DPRAM, that means only the buffers are on the 60x bus, and they are non-cacheable..SS "Known Problems".PPIf both the MOT_SCC_END and MOT_FCC_END driver are installed, the CPMDriver must be installed in endDevTbl[] first. This is a bug and probably has something to do with port pin set up order.Also, when using the N bootrom command to configure the MAC address, the motsccsysMotSccEnd driver always uses global mac address [1]. This fixes a problem with duplicate mac addresses. TrueFFS is supported with wrSbc8260Atm. The 64MB SIMM flash configuration is 8, 8MB(28F640Jx) devices. To configure TrueFFS #define INCLUDE_TFFS in config.h and add cfiscs.obj to MACH_EXTRA in the BSP Makefile..SH "BIBLIOGRAPHY".iB "MPC8260 PowerQUICC II User's Manual MPC8260UM/D".iB "PowerPC Microprocessor Family: The Programming Environments for 32-bit Microprocessors MPCFPE32B/AD".iB "MPC603e & EC603e RISC Microprocessors User's Manual MPC603EUM/AD"