/* m8260SccEnd.h - Motorola MPC8260 Serial Communication Controllers (SCC) Ethernet interface header *//* Copyright 1996-2001 Wind River Systems, Inc. *//*modification history--------------------01c,17may02,gjc  #SPR 75922, undef SCC_BUF if prev defined.01b,09may02,gjc  Fixing SPR #75046 by setting SCC to Full Duplex Mode.01a,10may01,g_h  adapted from sbcM8260CpmEnd.h (ver. 01b).*//*This file contains definitions to support the end-style Network Driver for the Motorola CPM core Ethernet controller used in the M68EN360 and PPC800-series communications controllers. These definitions are compilerdependant, meaning that their values are based on the particular cpubeing used.*/#ifndef __INCm8260SccEndh#define __INCm8260SccEndh#ifdef   __cplusplusextern "C" {#endif#include "drv/sio/m8260Cp.h"#include "drv/sio/m8260CpmMux.h"#include "drv/mem/m8260Siu.h"/* defines *//* * the following may be redefined in the bsp to account for the actual * number of SCC devices in the system. */#ifndef MAX_SCC_CHANNELS#define MAX_SCC_CHANNELS  4       /* max SCC number for Ethernet channels */#endif /* MAX_SCC_CHANNELS *//* MPC8260 Dual Ported Ram addresses */#define PPC8260_DPR_SCC1(dprbase)     ((VINT32 *) (dprbase + 0x8000))#define PPC8260_DPR_SCC2(dprbase)     ((VINT32 *) (dprbase + 0x8100))#define PPC8260_DPR_SCC3(dprbase)     ((VINT32 *) (dprbase + 0x8200))#define PPC8260_DPR_SCC4(dprbase)     ((VINT32 *) (dprbase + 0x8300))    /* SCC 1 register set */#define GSMR_L1(base)   (CAST(VUINT32 *)(base + 0x11A00)) /* SCC1 General Mode*/#define GSMR_H1(base)   (CAST(VUINT32 *)(base + 0x11A04)) /* SCC1 General Mode*/#define PSMR1(base)     (CAST(VUINT16 *)(base + 0x11A08)) /* SCC1 Proto. Spec *//* 11A0A RESERVED */#define TODR1(base)     (CAST(VUINT16 *)(base + 0x11A0C)) /* SCC1 Tx On Demand*/#define DSR1(base)      (CAST(VUINT16 *)(base + 0x11A0E)) /* SCC1 Data Sync */#define SCCE1(base)     (CAST(VUINT16 *)(base + 0x11A10)) /* SCC1 Event Reg */#define SCCM1(base)     (CAST(VUINT16 *)(base + 0x11A14)) /* SCC1 Mask Reg */#define SCCS1(base)     (CAST(VUINT8  *)(base + 0x11A17)) /* SCC1 Status Reg *//* 11A18-11A1F RESERVED *//* SCC 2 register set */#define GSMR_L2(base)   (CAST(VUINT32 *)(base + 0x11A20)) /* SCC2 General Mode*/#define GSMR_H2(base)   (CAST(VUINT32 *)(base + 0x11A24)) /* SCC2 General Mode*/#define PSMR2(base)     (CAST(VUINT16 *)(base + 0x11A28)) /* SCC2 Proto. Spec *//* 11A2A RESERVED */#define TODR2(base)     (CAST(VUINT16 *)(base + 0x11A2C)) /* SCC2 Tx On Demand*/#define DSR2(base)      (CAST(VUINT16 *)(base + 0x11A2E)) /* SCC2 Data Sync */#define SCCE2(base)     (CAST(VUINT16 *)(base + 0x11A30)) /* SCC2 Event Reg */#define SCCM2(base)     (CAST(VUINT16 *)(base + 0x11A34)) /* SCC2 Mask Reg */#define SCCS2(base)     (CAST(VUINT8  *)(base + 0x11A37)) /* SCC2 Status Reg *//* 11A38-11A3F RESERVED *//* SCC 3 register set */#define GSMR_L3(base)   (CAST(VUINT32 *)(base + 0x11A40)) /* SCC3 General Mode*/#define GSMR_H3(base)   (CAST(VUINT32 *)(base + 0x11A44)) /* SCC3 General Mode*/#define PSMR3(base)     (CAST(VUINT16 *)(base + 0x11A48)) /* SCC3 Proto. Spec *//* 11A4A RESERVED */#define TODR3(base)     (CAST(VUINT16 *)(base + 0x11A4C)) /* SCC3 Tx On Demand*/#define DSR3(base)      (CAST(VUINT16 *)(base + 0x11A4E)) /* SCC3 Data Sync */#define SCCE3(base)     (CAST(VUINT16 *)(base + 0x11A50)) /* SCC3 Event Reg */#define SCCM3(base)     (CAST(VUINT16 *)(base + 0x11A54)) /* SCC3 Mask Reg */#define SCCS3(base)     (CAST(VUINT8  *)(base + 0x11A57)) /* SCC3 Status Reg *//* 11A58-11A5F RESERVED *//* SCC 4 register set */#define GSMR_L4(base)   (CAST(VUINT32 *)(base + 0x11A60)) /* SCC4 General Mode*/#define GSMR_H4(base)   (CAST(VUINT32 *)(base + 0x11A64)) /* SCC4 General Mode*/#define PSMR4(base)     (CAST(VUINT16 *)(base + 0x11A68)) /* SCC4 Proto. Spec *//* 11A6A RESERVED */#define TODR4(base)     (CAST(VUINT16 *)(base + 0x11A6C)) /* SCC4 Tx On Demand*/#define DSR4(base)      (CAST(VUINT16 *)(base + 0x11A6E)) /* SCC4 Data Sync */#define SCCE4(base)     (CAST(VUINT16 *)(base + 0x11A70)) /* SCC4 Event Reg */#define SCCM4(base)     (CAST(VUINT16 *)(base + 0x11A74)) /* SCC2 Mask Reg */#define SCCS4(base)     (CAST(VUINT8  *)(base + 0x11A77)) /* SCC4 Status Reg *//* 11A78-11A7F RESERVED */#define SCC_USR_RUNNING_FROM_ROM    0x00000001  /* inhibit zcopy mode */#define CPM_DPR_SCC1(baseAddr)  PPC8260_DPR_SCC1 (baseAddr)#define CPM_GSMR_L1(baseAddr)   GSMR_L1 (baseAddr)#define END_OBJ_STRING  "MPC8260 PowerQUICC II Enhanced Network Driver"#define MOT_DEV_NAME    "motscc"#define MOT_DEV_NAME_LEN 7/* bsp-specific routine to include */#define SYS_ENET_ADDR_GET(address)                                      \if (sysSccEnetAddrGet != NULL)                                          \    if (sysSccEnetAddrGet (pDrvCtrl->unit, (address)) == ERROR)         \        {                                                               \        errnoSet (S_iosLib_INVALID_ETHERNET_ADDRESS);                   \        return (NULL);                                                  \        } #define SYS_ENET_ENABLE                                                 \if (sysSccEnetEnable != NULL)                                           \    if (sysSccEnetEnable (pDrvCtrl->unit) == ERROR)                     \        return (ERROR); #define SYS_ENET_DISABLE                                                \if (sysSccEnetDisable != NULL)                                          \    sysSccEnetDisable (pDrvCtrl->unit);/* General SCC Mode Register definitions */#define SCC_GSMRL_HDLC          0x00000000      /* HDLC mode */#define SCC_GSMRL_APPLETALK     0x00000002      /* AppleTalk mode (LocalTalk) */#define SCC_GSMRL_SS7           0x00000003      /* SS7 mode (microcode) */#define SCC_GSMRL_UART          0x00000004      /* UART mode */#define SCC_GSMRL_PROFI_BUS     0x00000005      /* Profi-Bus mode (microcode) */#define SCC_GSMRL_ASYNC_HDLC    0x00000006      /* async HDLC mode (microcode)*/#define SCC_GSMRL_V14           0x00000007      /* V.14 mode */#define SCC_GSMRL_BISYNC        0x00000008      /* BISYNC mode */#define SCC_GSMRL_DDCMP         0x00000009      /* DDCMP mode (microcode) */#define SCC_GSMRL_ETHERNET      0x0000000c      /* ethernet mode (SCC1 only) */#define SCC_GSMRL_ENT           0x00000010      /* enable transmitter */#define SCC_GSMRL_ENR           0x00000020      /* enable receiver */#define SCC_GSMRL_LOOPBACK      0x00000040      /* local loopback mode */#define SCC_GSMRL_ECHO          0x00000080      /* automatic echo mode */#define SCC_GSMRL_TENC          0x00000700      /* transmitter encoding method*/#define SCC_GSMRL_RENC          0x00003800      /* receiver encoding method */#define SCC_GSMRL_RDCR_X8       0x00004000      /* receive DPLL clock x8 */#define SCC_GSMRL_RDCR_X16      0x00008000      /* receive DPLL clock x16 */#define SCC_GSMRL_RDCR_X32      0x0000c000      /* receive DPLL clock x32 */#define SCC_GSMRL_TDCR_X8       0x00010000      /* transmit DPLL clock x8 */#define SCC_GSMRL_TDCR_X16      0x00020000      /* transmit DPLL clock x16 */#define SCC_GSMRL_TDCR_X32      0x00030000      /* transmit DPLL clock x32 */#define SCC_GSMRL_TEND          0x00040000      /* transmitter frame ending */#define SCC_GSMRL_TPP_00        0x00180000      /* Tx preamble pattern = 00 */#define SCC_GSMRL_TPP_10        0x00080000      /* Tx preamble pattern = 10 */#define SCC_GSMRL_TPP_01        0x00100000      /* Tx preamble pattern = 01 */#define SCC_GSMRL_TPP_11        0x00180000      /* Tx preamble pattern = 11 */#define SCC_GSMRL_TPL_NONE      0x00000000      /* no Tx preamble (default) */#define SCC_GSMRL_TPL_8         0x00200000      /* Tx preamble = 1 byte */#define SCC_GSMRL_TPL_16        0x00400000      /* Tx preamble = 2 bytes */#define SCC_GSMRL_TPL_32        0x00600000      /* Tx preamble = 4 bytes */#define SCC_GSMRL_TPL_48        0x00800000      /* Tx preamble = 6 bytes */#define SCC_GSMRL_TPL_64        0x00a00000      /* Tx preamble = 8 bytes */#define SCC_GSMRL_TPL_128       0x00c00000      /* Tx preamble = 16 bytes */#define SCC_GSMRL_TINV          0x01000000      /* DPLL transmit input invert */#define SCC_GSMRL_RINV          0x02000000      /* DPLL receive input invert */#define SCC_GSMRL_TSNC          0x0c000000      /* transmit sense */#define SCC_GSMRL_TCI           0x10000000      /* transmit clock invert */#define SCC_GSMRL_EDGE          0x60000000      /* adjustment edge +/- */ #define SCC_GSMRH_RSYN          0x00000001      /* receive sync timing*/#define SCC_GSMRH_RTSM          0x00000002      /* RTS* mode */#define SCC_GSMRH_SYNL          0x0000000c      /* sync length */#define SCC_GSMRH_TXSY          0x00000010      /* transmitter/receiver sync */#define SCC_GSMRH_RFW           0x00000020      /* Rx FIFO width */#define SCC_GSMRH_TFL           0x00000040      /* transmit FIFO length */#define SCC_GSMRH_CTSS          0x00000080      /* CTS* sampling */#define SCC_GSMRH_CDS           0x00000100      /* CD* sampling */#define SCC_GSMRH_CTSP          0x00000200      /* CTS* pulse */#define SCC_GSMRH_CDP           0x00000400      /* CD* pulse */#define SCC_GSMRH_TTX           0x00000800      /* transparent transmitter */#define SCC_GSMRH_TRX           0x00001000      /* transparent receiver */#define SCC_GSMRH_REVD          0x00002000      /* reverse data */#define SCC_GSMRH_TCRC          0x0000c000      /* transparent CRC */#define SCC_GSMRH_GDE           0x00010000      /* glitch detect enable *//* CPM - Communication Processor Module *//* SCC Ethernet Protocol Specific Mode Register definitions */ #define SCC_ETHER_PSMR_FDE      0x0001#define SCC_ETHER_PSMR_NIB_13   0x0000          /* SFD 13 bits after TENA */#define SCC_ETHER_PSMR_NIB_14   0x0002          /* SFD 14 bits after TENA */#define SCC_ETHER_PSMR_NIB_15   0x0004          /* SFD 15 bits after TENA */#define SCC_ETHER_PSMR_NIB_16   0x0006          /* SFD 16 bits after TENA */#define SCC_ETHER_PSMR_NIB_21   0x0008          /* SFD 21 bits after TENA */#define SCC_ETHER_PSMR_NIB_22   0x000a          /* SFD 22 bits after TENA */