#define SCC_ETHER_PSMR_NIB_23   0x000c          /* SFD 23 bits after TENA */#define SCC_ETHER_PSMR_NIB_24   0x000e          /* SFD 24 bits after TENA */#define SCC_ETHER_PSMR_LCW      0x0010          /* late collision window */#define SCC_ETHER_PSMR_SIP      0x0200          /* sample input pins */#define SCC_ETHER_PSMR_LPB      0x0040          /* loopback operation */#define SCC_ETHER_PSMR_SBT      0x0080          /* stop backoff timer */#define SCC_ETHER_PSMR_BRO      0x0100          /* broadcast address */#define SCC_ETHER_PSMR_PRO      0x0200          /* promiscuous mode */#define SCC_ETHER_PSMR_CRC      0x0800          /* CRC selection */#define SCC_ETHER_PSMR_IAM      0x1000          /* individual address mode */#define SCC_ETHER_PSMR_RSH      0x2000          /* receive short frame */#define SCC_ETHER_PSMR_FC       0x4000          /* force collision */#define SCC_ETHER_PSMR_HBC      0x8000          /* heartbeat checking*/ /* SCC Ethernet Event and Mask Register definitions */ #define SCC_ETHER_SCCX_RXB      0x0001          /* buffer received event */#define SCC_ETHER_SCCX_TXB      0x0002          /* buffer transmitted event */#define SCC_ETHER_SCCX_BSY      0x0004          /* busy condition */#define SCC_ETHER_SCCX_RXF      0x0008          /* frame received event */#define SCC_ETHER_SCCX_TXE      0x0010          /* transmission error event */#define SCC_ETHER_SCCX_GRA      0x0080          /* graceful stop event */ /* SCC Ethernet Receive Buffer Descriptor definitions */ #define SCC_ETHER_RX_BD_CL      0x0001          /* collision condition */#define SCC_ETHER_RX_BD_OV      0x0002          /* overrun condition */#define SCC_ETHER_RX_BD_CR      0x0004          /* Rx CRC error */#define SCC_ETHER_RX_BD_SH      0x0008          /* short frame received */#define SCC_ETHER_RX_BD_NO      0x0010          /* Rx nonoctet aligned frame */#define SCC_ETHER_RX_BD_LG      0x0020          /* Rx frame length violation */#define SCC_ETHER_RX_BD_M       0x0100          /* miss bit for prom mode */#define SCC_ETHER_RX_BD_F       0x0400          /* buffer is first in frame */#define SCC_ETHER_RX_BD_L       0x0800          /* buffer is last in frame */#define SCC_ETHER_RX_BD_I       0x1000          /* interrupt on receive */#define SCC_ETHER_RX_BD_W       0x2000          /* last BD in ring */#define SCC_ETHER_RX_BD_E       0x8000          /* buffer is empty */ /* SCC Ethernet Transmit Buffer Descriptor definitions */ #define SCC_ETHER_TX_BD_CSL     0x0001          /* carrier sense lost */#define SCC_ETHER_TX_BD_UN      0x0002          /* underrun */#define SCC_ETHER_TX_BD_RC      0x003c          /* retry count */#define SCC_ETHER_TX_BD_RL      0x0040          /* retransmission limit */#define SCC_ETHER_TX_BD_LC      0x0080          /* late collision */#define SCC_ETHER_TX_BD_HB      0x0100          /* heartbeat */#define SCC_ETHER_TX_BD_DEF     0x0200          /* defer indication */#define SCC_ETHER_TX_BD_TC      0x0400          /* auto transmit CRC */#define SCC_ETHER_TX_BD_L       0x0800          /* buffer is last in frame */#define SCC_ETHER_TX_BD_I       0x1000          /* interrupt on transmit */#define SCC_ETHER_TX_BD_W       0x2000          /* last BD in ring */#define SCC_ETHER_TX_BD_PAD     0x4000          /* auto pad short frames */#define SCC_ETHER_TX_BD_R       0x8000          /* buffer is ready *//* typedefs *//* SCC - Serial Comunications Controller */typedef struct          /* SCC_ETHER_PROTO */    {    UINT32      c_pres;                 /* preset CRC */    UINT32      c_mask;                 /* constant mask for CRC */    UINT32      crcec;                  /* CRC error counter */    UINT32      alec;                   /* alignment error counter */    UINT32      disfc;                  /* discard frame counter */    UINT16      pads;                   /* short frame pad value */    UINT16      ret_lim;                /* retry limit threshold */    UINT16      ret_cnt;                /* retry limit counter */    UINT16      mflr;                   /* maximum frame length register */    UINT16      minflr;                 /* minimum frame length register */    UINT16      maxd1;                  /* max DMA1 length register */    UINT16      maxd2;                  /* max DMA2 length register */    UINT16      maxd;                   /* Rx max DMA */    UINT16      dma_cnt;                /* Rx DMA counter */    UINT16      max_b;                  /* max BD byte count */    UINT16      gaddr1;                 /* group address filter 1 */    UINT16      gaddr2;                 /* group address filter 2 */    UINT16      gaddr3;                 /* group address filter 3 */    UINT16      gaddr4;                 /* group address filter 4 */    UINT32      tbuf0_data0;            /* save area 0 - current frame */    UINT32      tbuf0_data1;            /* save area 1 - current frame */    UINT32      tbuf0_rba0;             /* ? */    UINT32      tbuf0_crc;              /* ? */    UINT16      tbuf0_bcnt;             /* ? */    UINT16      paddr1_h;               /* physical address 1 (MSB) */    UINT16      paddr1_m;               /* physical address 1 */    UINT16      paddr1_l;               /* physical address 1 (LSB) */    UINT16      p_per;                  /* persistence */    UINT16      rfbd_ptr;               /* Rx first BD pointer */    UINT16      tfbd_ptr;               /* Tx first BD pointer */    UINT16      tlbd_ptr;               /* Tx last BD pointer */    UINT32      tbuf1_data0;            /* save area 0 - next frame */    UINT32      tbuf1_data1;            /* ? */    UINT32      tbuf1_rba0;             /* ? */    UINT32      tbuf1_crc;              /* ? */    UINT16      tbuf1_bcnt;             /* ? */    UINT16      tx_len;                 /* Tx frame length counter */    UINT16      iaddr1;                 /* individual address filter 1 */    UINT16      iaddr2;                 /* individual address filter 2 */    UINT16      iaddr3;                 /* individual address filter 3 */    UINT16      iaddr4;                 /* individual address filter 4 */    UINT16      boff_cnt;               /* backoff counter */    UINT16      taddr_h;                /* temp address (MSB) */    UINT16      taddr_m;                /* temp address */    UINT16      taddr_l;                /* temp address (LSB) */    } SCC_ETHER_PROTO;/* SCC Parameters */    typedef struct          /* SCC_PARAM */        {                   /* offset description*/        volatile INT16  rbase;      /* 00 Rx buffer descriptor base address */        volatile INT16  tbase;      /* 02 Tx buffer descriptor base address */        volatile INT8   rfcr;       /* 04 Rx function code */        volatile INT8   tfcr;       /* 05 Tx function code */        volatile INT16  mrblr;      /* 06 maximum receive buffer length */        volatile INT32  rstate;     /* 08 Rx internal state */        volatile INT32  res1;       /* 0C Rx internal data pointer */        volatile INT16  rbptr;      /* 10 Rx buffer descriptor pointer */        volatile INT16  res2;       /* 12 reserved/internal */        volatile INT32  res3;       /* 14 reserved/internal */        volatile INT32  tstate;     /* 18 Tx internal state */        volatile INT32  res4;       /* 1C reserved/internal */        volatile INT16  tbptr;      /* 20 Tx buffer descriptor pointer */        volatile INT16  res5;       /* 22 reserved/internal */        volatile INT32  res6;       /* 24 reserved/internal */        volatile INT32  rcrc;       /* 28 temp receive CRC */        volatile INT32  tcrc;       /* 2C temp transmit CRC */        } SCC_PARAM;   typedef struct          /* SCC */    {    SCC_PARAM   param;                  /* SCC parameters */    char        prot[64];               /* protocol specific area */    } SCC;typedef struct          /* SCC_REG */    {    UINT32      gsmrl;                  /* SCC general mode register - low */    UINT32      gsmrh;                  /* SCC eneral mode register - high */    UINT16      psmr;                   /* SCC protocol mode register */    UINT16      res1;                   /* reserved */    UINT16      todr;                   /* SCC transmit on demand */    UINT16      dsr;                    /* SCC data sync. register */    UINT16      scce;                   /* SCC event register */    UINT16      res2;                   /* reserved */    UINT16      sccm;                   /* SCC mask register */    UINT8       res3;                   /* reserved */    UINT8       sccs;                   /* SCC status register */    } SCC_REG;/* SCC Buffer */#ifdef SCC_BUF#undef SCC_BUF#endiftypedef struct          /* SCC_BUF */    {    UINT16      statusMode;     /* status and control */    UINT16      dataLength;     /* length of data buffer in bytes */    u_char  *   dataPointer;    /* points to data buffer */    } SCC_BUF;/* SCC device descriptor */typedef struct          /* SCC_ETHER_DEV */    {    int                 sccNum;         /* number of SCC device */    int                 txBdNum;        /* number of transmit buf descriptors */    int                 rxBdNum;        /* number of receive buf descriptors */    SCC_BUF *           txBdBase;       /* transmit BD base address */    SCC_BUF *           rxBdBase;       /* receive BD base address */    u_char *            txBufBase;      /* transmit buffer base address */    u_char *            rxBufBase;      /* receive buffer base address */    UINT32              txBufSize;      /* transmit buffer size */    UINT32              rxBufSize;      /* receive buffer size */    int                 txBdNext;       /* next transmit BD to fill */    int                 rxBdNext;       /* next receive BD to read */    volatile SCC *      pScc;           /* SCC parameter RAM */    volatile SCC_REG *  pSccReg;        /* SCC registers */    UINT32              intMask;        /* interrupt acknowledge mask */    } SCC_ETHER_DEV;/* globals */ IMPORT STATUS sysSccEnetEnable  (int unit); /* enable ctrl */IMPORT void   sysSccEnetDisable (int unit); /* disable ctrl */IMPORT STATUS sysSccEnetAddrGet (int unit, u_char * addr);  /* get enet addr */#ifdef  __cplusplus}#endif#endif  /* __INCm8260SccEndh */