/* romInit.s - SBC8260ATM ROM initialization module *//* Copyright 1984-2001 Wind River Systems, Inc. */	.data	.globl  copyright_wind_river	.long   copyright_wind_river/*modification history--------------------01a,21jun01,g_h  created from sbc8260/romInit.s (ver 01b).*//*DESCRIPTIONThis module contains the entry code for the VxWorks bootrom.The entry point romInit, is the first code executed on power-up.It sets the BOOT_COLD parameter to be passed to the genericromStart() routine.The routine sysToMonitor() jumps to the location 4 bytespast the beginning of romInit, to perform a "warm boot".This entry point allows a parameter to be passed to romStart().*/#define	_ASMLANGUAGE#include "vxWorks.h"#include "asm.h"#include "cacheLib.h"#include "config.h"#include "wrSbc8260Atm.h"#include "regs.h"#include "sysLib.h"#include "config.h"#include "drv/timer/m8260Clock.h"#include "drv/mem/m8260Siu.h"#include "drv/mem/m8260Memc.h"		/* internals */	.globl	_romInit	/* start of system code */	.globl	romInit		/* start of system code */		/* externals */	.extern romStart	/* system initialization routine */	.text	.align 2/******************************************************************************** romInit - entry point for VxWorks in ROM*** romInit*     (*     int startType	/@ only used by 2nd entry point @/*     )*/_romInit:romInit:	bl	cold		/* jump to the cold boot initialization */	nop	bl	start		/* jump to the warm boot initialization */	/* copyright notice appears at beginning of ROM (in TEXT segment) */	.ascii   "Copyright 1984-1999 Wind River Systems, Inc."	.align 2cold:	li	    r3,BOOT_COLD	/* set cold boot as start type */start:    /* disable external interrupts (by zeroing out msr) */	xor	    r5,r5,r5	isync  	mtmsr	r5	isync      /* invalidate and disable the MPU's data/instruction caches */	mfspr	r6,HID0	ori	    r5,r5,0xC000	andc	r6,r6,r5	 /* clear cache enable bits in r6 */	mr	    r5,r6	ori	    r5,r5,0xCC00 /* r5 has DCE,ICE,ICFI,DCFI set */	sync	mtspr	HID0,r5		 /* invalidate both caches with 2 stores */	mtspr	HID0,r6		 /* leaving them both disabled */	isync	mtspr   SPRG0,r3	bl	    romClearBATs	bl	    romInvalidateTLBs	bl	    romClearSegs	bl	    romClearFPRegs	mfspr   r3,SPRG0        /* Zero-out registers: r0 & SPRGs */    xor	    r0,r0,r0	mtspr	SPRG0,r0	mtspr	SPRG1,r0	mtspr	SPRG2,r0	mtspr	SPRG3,r0    /* MSR: clear DCE,ICE,EE,DR,IR -- set ME,RI	*/	mfmsr   r4	ori	    r4,r0,0x1002	mtmsr   r4	isync 	/*	 * initialize the IMMR register before any non-core registers	 * modification.	 */	lis	    r4, HIADJ(INTERNAL_MEM_MAP_ADDR+0x10000)	addi	r4, r4, LO(INTERNAL_MEM_MAP_ADDR+0x10000)	sync	lis	    r5, HIADJ(INTERNAL_MEM_MAP_ADDR)	addi	r5, r5, LO(INTERNAL_MEM_MAP_ADDR)	sync	stw	    r5, INIT_IMMR(r4)		/* initialize the IMMR register */	/********************************************************	 * initialize the SIU.	 ********************************************************/	bl	romSiuInit	/********************************************************	 * initialize the MEMC.	 ********************************************************/	bl	romMemcInit	/****************************************************	 * Initialize Instruction and Data Caches	 ****************************************************/	bl	romCacheInit    /* initialize the stack pointer */	lis	    sp, HIADJ(STACK_ADRS)	addi	sp, sp, LO(STACK_ADRS)		/* go to C entry point */	addi	sp, sp, -FRAMEBASESZ		/* get frame stack */	/* 	 * calculate C entry point: routine - entry point + ROM base 	 * routine	= romStart	= R6	 * entry point	= romInit	= R7	 * ROM base	= ROM_TEXT_ADRS = R8	 * C entry point: R6 - R7 + R8 	 */    lis	    r6, HIADJ(romStart)	    addi	r6, r6, LO(romStart)	/* load R6 with C entry point */	lis	    r7, HIADJ(romInit)	addi	r7, r7, LO(romInit)	lis	    r8, HIADJ(ROM_TEXT_ADRS)	addi	r8, r8, LO(ROM_TEXT_ADRS)	sub	    r6, r6, r7	/* routine - entry point */	add	    r6, r6, r8 	/* + ROM base */	mtlr	r6			/* move C entry point to LR */	blr		    		/* jump to the C entry point *//********************************************************************************* romClearBATs - ** This routine will zero the BAT registers.** RETURNS: None**/romClearBATs:			/* zero out the BAT registers */	xor		r5,r5,r5	isync	mtspr	IBAT0U,r5	/* clear all upper BATS first */	mtspr	IBAT1U,r5	mtspr	IBAT2U,r5	mtspr	IBAT3U,r5	mtspr	DBAT0U,r5	mtspr	DBAT1U,r5	mtspr	DBAT2U,r5	mtspr	DBAT3U,r5	mtspr	IBAT0L,r5	/* then clear lower BATS */	mtspr	IBAT1L,r5	mtspr	IBAT2L,r5	mtspr	IBAT3L,r5	mtspr	DBAT0L,r5	mtspr	DBAT1L,r5	mtspr	DBAT2L,r5	mtspr	DBAT3L,r5	isync	blr/********************************************************************************* romClearSegs - ** This routine will zero the MMU's segment registers.** RETURNS: None**/romClearSegs:		/* Init the Segment registers */	xor		r5, r5, r5    isync    mtsr	0,r5    mtsr    1,r5    mtsr    2,r5    mtsr    3,r5    mtsr    4,r5    mtsr    5,r5	mtsr    6,r5    mtsr    7,r5    mtsr    8,r5    mtsr    9,r5    mtsr    10,r5    mtsr    11,r5    mtsr    12,r5    mtsr    13,r5    mtsr    14,r5    mtsr    15,r5    isync	blr/********************************************************************************* romInvalidateTLBs - ** This routine will invalidate the BAT's register.** RETURNS: None**/romInvalidateTLBs:	isync	/* invalidate entries within both TLBs */	li		r5,128	mtctr	r5		  /* CTR = 32  */	xor		r5,r5,r5  /* r5 = 0    */	isync			  /* context sync req'd before tlbie */tlbloop:	tlbie	r5	sync			     /* sync instr req'd after tlbie      */	addi	r5,r5,0x1000 /* increment bits 15-19 */	bdnz	tlbloop		 /* decrement CTR, branch if CTR != 0 */	isync	blr/********************************************************************************* romClearFPRegs** This routine will initialize the FPU's registers.** RETURNS: None**/romClearFPRegs:	mflr	r30		/* Turn on FP */    li	    r3,0x2000    mtmsr   r3    sync    /* Init the floating point control/status register */    mtfsfi  7,0x0    mtfsfi  6,0x0    mtfsfi  5,0x0    mtfsfi  4,0x0    mtfsfi  3,0x0    mtfsfi  2,0x0    mtfsfi  1,0x0    mtfsfi  0,0x0    isync    /* Initialize the floating point data registers to a known state */    bl      ifpdrValue    .long   0x3f800000      /* 1.0 */ifpdrValue:    mflr    r3    lfs     f0,0(r3)    lfs     f1,0(r3)    lfs     f2,0(r3)    lfs     f3,0(r3)    lfs     f4,0(r3)    lfs     f5,0(r3)    lfs     f6,0(r3)    lfs     f7,0(r3)    lfs     f8,0(r3)    lfs     f9,0(r3)    lfs     f10,0(r3)    lfs     f11,0(r3)    lfs     f12,0(r3)    lfs     f13,0(r3)    lfs     f14,0(r3)    lfs     f15,0(r3)    lfs     f16,0(r3)    lfs     f17,0(r3)    lfs     f18,0(r3)    lfs     f19,0(r3)    lfs     f20,0(r3)    lfs     f21,0(r3)    lfs     f22,0(r3)    lfs     f23,0(r3)    lfs     f24,0(r3)    lfs     f25,0(r3)    lfs     f26,0(r3)    lfs     f27,0(r3)    lfs     f28,0(r3)    lfs     f29,0(r3)    lfs     f30,0(r3)    lfs     f31,0(r3)    sync    /*     *     Set MPU/MSR to a known state     *     Turn off FP     */    andi.  r3,r3,0    sync    mtmsr  r3    isync		mtlr	r30	bclr	20,0		/* Return to caller *//******************************************************************************** romSiuInit - initialize the general SIU.*** RETURNS: N/A.*/romSiuInit:	lis	    r5,HIADJ(0x0E240000)	addi	r5,r5,LO(0x0E240000)	stw		r5,INIT_SIUMCR(r4)	lis	    r5,HIADJ(0xFFFFFFC3)	addi	r5,r5,LO(0xFFFFFFC3)	stw		r5,INIT_SYPCR(r4)	lis	    r5,HIADJ(0xFFFF0000)	addi	r5,r5,LO(0xFFFF0000)	stw		r5,INIT_SWT(r4)	lis	    r5,HIADJ(0x0000000E)	addi	r5,r5,LO(0x0000000E)	sth		r5,INIT_SWSR(r4)	lis	    r5,HIADJ(0x00000000)	addi	r5,r5,LO(0x00000000)	stw		r5,INIT_BCR(r4)	li	    r5,0x02	stb	    r5,INIT_PPC_ACR(r4)	lis	    r5,HIADJ(0x01234567)	addi	r5,r5,LO(0x01234567)	stw		r5,INIT_PPC_ALRH(r4)	lis	    r5,HIADJ(0x89ABCDEF)	addi	r5,r5,LO(0x89ABCDEF)	stw		r5,INIT_PPC_ALRL(r4)	li		r5,0x02		stb		r5,INIT_LCL_ACR(r4)	lis	    r5,HIADJ(0x01234567)	addi	r5,r5,LO(0x01234567)	stw		r5,INIT_LCL_ALRH(r4)	lis	    r5,HIADJ(0x89ABCDEF)	addi	r5,r5,LO(0x89ABCDEF)	stw		r5,INIT_LCL_ALRL(r4)	lis 	r5,HIADJ(0x80020000)	addi	r5,r5,LO(0x80020000)	stw		r5,INIT_TESCR1(r4)	lis 	r5,HIADJ(0x00000000)	addi	r5,r5,LO(0x00000000)	stw		r5,INIT_TESCR2(r4)	lis 	r5,HIADJ(0x00000000)	addi	r5,r5,LO(0x00000000)	stw		r5,INIT_LTESCR1(r4)	lis 	r5,HIADJ(0x00000000)	addi	r5,r5,LO(0x00000000)	stw		r5,INIT_LTESCR2(r4)    lis	    r5, HIADJ(M8260_SCCR_DFBRG_4)  /* divide by 4 */	addi	r5, r5, LO(M8260_SCCR_DFBRG_4) /* divide by 4 */	stw	    r5, INIT_SCCR(r4)	lis	    r5,HIADJ(0x00000000)	addi	r5,r5,LO(0x00000000)	stw		r5,INIT_PDTEA(r4)	li  	r5,0x00	stb	    r5,INIT_PDTEM(r4)	lis	    r5,HIADJ(0x00000000)	addi	r5,r5,LO(0x00000000)	stw		r5,INIT_LDTEA(r4)	li  	r5,0x00	stb	    r5,INIT_LDTEM(r4)	bclr   20,0/******************************************************************************** romMemcInit - initialize the memory controller and SDRAM.*** RETURNS: N/A.*/romMemcInit:	mfspr	r30,LR	bl romChipSelectInit	lis	    r5,HIADJ(0x00000200)	addi	r5,r5,LO(0x00000200)	stw		r5,INIT_MAR(r4)	lis	    r5,HIADJ(0x00000000)	addi	r5,r5,LO(0x00000000)	stw		r5,INIT_MAMR(r4)	lis	    r5,HIADJ(0x00000000)