#define ECR_EMAC_RX_3           0x60000000     /* 405GPr only     */#define ECR_EMAC_RX_4           0x80000000     /* 405GPr only     */#define ECR_EMAC_RX_6           0xA0000000     /* 405GPr only     */#define ECR_EMAC_RX_8           0xC0000000     /* 405GPr only     */#define ECR_EMAC_RX_10          0xE0000000     /* 405GPr only     */#define ECR_EMAC_TX_MASK        0x00E00000     /* 405GPr only     */#define ECR_EMAC_TX_BYP         0x00000000     /* 405GPr only     */#define ECR_EMAC_TX_1           0x00200000     /* 405GPr only     */#define ECR_EMAC_TX_2           0x00400000     /* 405GPr only     */#define ECR_EMAC_TX_3           0x00600000     /* 405GPr only     */#define ECR_EMAC_TX_4           0x00800000     /* 405GPr only     */#define ECR_EMAC_TX_6           0x00A00000     /* 405GPr only     */#define ECR_EMAC_TX_8           0x00C00000     /* 405GPr only     */#define ECR_EMAC_TX_10          0x00E00000     /* 405GPr only     */#define ECR_UIC_MASK            0x0000E000     /* 405GPr only     */#define ECR_UIC_BYP             0x00000000     /* 405GPr only     */#define ECR_UIC_1               0x00002000     /* 405GPr only     */#define ECR_UIC_2               0x00004000     /* 405GPr only     */#define ECR_UIC_3               0x00006000     /* 405GPr only     */#define ECR_UIC_4               0x00008000     /* 405GPr only     */#define ECR_UIC_6               0x0000A000     /* 405GPr only     */#define ECR_UIC_8               0x0000C000     /* 405GPr only     */#define ECR_UIC_10              0x0000E000     /* 405GPr only     *//* * On-chip memory controller configuration register definitions. */#define OCM_ISARC  (OCM_DCR_BASE+0x00)    /* Instruction-side Addr range cmp  */#define OCM_ISCNTL (OCM_DCR_BASE+0x01)    /* Instruction-side control reg     */#define OCM_DSARC  (OCM_DCR_BASE+0x02)    /* Data-side Addr range cmp         */#define OCM_DSCNTL (OCM_DCR_BASE+0x03)    /* Data-side control reg            *//* OCM register bits */#define OCM_DSAR    0xFC000000            /* OCM D-side address mask          */#define OCM_DSEN    0x80000000            /* OCM D-side enable                */#define OCM_ISAR    0xFC000000            /* OCM I-side address mask          */#define OCM_ISEN    0x80000000            /* OCM I-side enable                */#define OCM_ISTCM   0x40000000            /* OCM I-side 2 cycle mode          *//* * CodePack Code Decompression core register definitions. Two DCRs are used * (address/data) to indirectly access the config registers of this controller. */#define DCP_CFGADDR (DECOMP_DCR_BASE+0x0)  /* Decompression cntrl addr reg    */#define DCP_CFGDATA (DECOMP_DCR_BASE+0x1)  /* Decompression cntrl data reg    */  /* values for DCP_CFGADDR register - indirect addressing of these regs */  #define DCP_ITOR0   0x00    /* index table origin register 0        */  #define DCP_ITOR1   0x01    /* index table origin register 1        */  #define DCP_ITOR2   0x02    /* index table origin register 2        */  #define DCP_ITOR3   0x03    /* index table origin register 3        */  #define DCP_ADDR0   0x04    /* address decode definition regsiter 0 */  #define DCP_ADDR1   0x05    /* address decode definition regsiter 1 */  #define DCP_CFG     0x40    /* decompression core config register   */  #define DCP_ID      0x41    /* decompression core ID     register   */  #define DCP_VER     0x42    /* decompression core version # reg     */  #define DCP_PLBBEAR 0x50    /* bus error addr reg (PLB addr)        */  #define DCP_MEMBEAR 0x51    /* bus error addr reg (DCP to EBIU addr)*/  #define DCP_ESR     0x52    /* bus error status reg 0  (R/clear)    */  /* There are 0x400 of the following registers, from 0x400 to 0x7ff  */  /* Only the first and last ones are defined here.                   */  #define DCP_RAM0   0x400    /* SRAM/ROM read/write (first location) */  #define DCP_RAM3FF 0x7FF    /* SRAM/ROM read/write (last location)  *//* * PLB Bus Error, Arbiter and PLB to OPB Bridge DCR registers. */#define PLB_BESR      0x84    /* PLB Error Status Reg                 */#define PLB_BEAR      0x86    /* PLB Error Address Reg                */#define PLB_ACR       0x87    /* PLB Arbiter Control Reg              */#define POB_BESR0     0xa0    /* PLB to OPB Bridge Error Status Reg 0 */#define POB_BEAR      0xa2    /* PLB to OPB Bridge Error Address Reg  */#define POB_BESR1     0xa4    /* PLB to OPB Bridge Error Status Reg 1 *//* * OPB Bus Arbiter registers (memory mapped) */#define OPBA_PR       0xEF600600     /* OPB Arbiter Priority Register */#define OPBA_CR       0xEF600601     /* OPB Aribter Control Register  *//* * 405GP IIC Base Address definition and register offsets. */#define IIC0_BASE       0xEF600500#define    IIC_MDBUF         0x00#define    IIC_SDBUF         0x02#define    IIC_LMADR         0x04#define    IIC_HMADR         0x05#define    IIC_CNTL          0x06#define    IIC_MDCNTL        0x07#define    IIC_STS           0x08#define    IIC_EXTSTS        0x09#define    IIC_LSADR         0x0A#define    IIC_HSADR         0x0B#define    IIC_CLKDIV        0x0C#define    IIC_INTRMSK       0x0D#define    IIC_XFRCNT        0x0E#define    IIC_XTCNTLSS      0x0F#define    IIC_DIRECTCNTL    0x10/* * 405GP UART (2 of them) Base Address definitions.  Both UARTs are 16550-like. */#define UART0_BASE      0xEF600300#define UART1_BASE      0xEF600400#define UART_REG_ADDR_INTERVAL   1#define UART_MEMORY_START   0xEF600000#define UART_MEMORY_END     0xEF600FFF/* * 405GP PCI address map *//* * PCI memory space from the PLB. * PLB to PCI address translation is controlled by the 3 pairs of PTM registers. */#define PCI_MEMORY_START            0x80000000#define PCI_MEMORY_END              0xE7FFFFFF/* * For the MMU to conserve page table space, we map only 64 MB of the PCI * memory space (needed by VGA card). */#define PCI_MEMORY_MAP_END      0x83FFFFFF  /* 64 MB mapped in MMU *//* * PCI I/O space from the PLB and the PCI translation. */#define PLB_PCI_IO_REGION_1_START   0xE8000000     /* PLB side */#define PLB_PCI_IO_REGION_1_END     0xE800FFFF#define PLB_PCI_IO_REGION_1_SIZE    0x00010000#define PLB_PCI_IO_REGION_2_START   0xE8800000#define PLB_PCI_IO_REGION_2_END     0xEBFFFFFF#define PLB_PCI_IO_REGION_2_SIZE    0x03800000#define PLB_PCI_IO_REGION_2_MAP_END 0xE88FFFFF     /* 1 MB mapped in MMU */                           						   /* increase if needed */#define PCI_IO_REGION_1_START       0x00000000     /* PCI side */#define PCI_IO_REGION_1_END         0x0000FFFF#define PCI_IO_REGION_2_START       0x00800000#define PCI_IO_REGION_2_END         0x03FFFFFF#define PCI_INTERRUPT_ACK           0xEED00000     /* read */#define PCI_SPECIAL_CYCLE           0xEED00000     /* write */#define PCI_INTERRUPT_ACK_END       0xEED00FFF     /* 1 page in MMU *//* * Register pair used to generate configuration cycles on the PCI bus * and access the 405GP's own PCI configuration registers. */#define PCI_CFGADDR        0xEEC00000#define PCI_CFGDATA        0xEEC00004#define PCI_CFGEND         0xEEC00FFF  /* 1 page in MMU *//* * PP Bridge Local Config registers space */#define PP_BRIDGE_CR        0xEF400000#define PP_BRIDGE_CR_END    0xEF400FFF  /* 1 page in MMU *//* * Register addresses for the 3 sets of 405GP PCI Master Mode (PMM) * local configuration registers.  These registers control how local memory * addresses are translated to PCI memory addresses when the 405GP is a * PCI bus master (initiator).  The contents of the PMMxLA register must be * set to an address that is within the 405GP PCI memory range * (PCI_MEMORY_START - PCI_MEMORY_END). */#define PCIL_PMM0LA        0xEF400000       /* Local Address                  */#define PCIL_PMM0MA        0xEF400004       /* Mask/Attribute register        */#define PCIL_PMM0PCILA     0xEF400008       /* Local address is translated to */#define PCIL_PMM0PCIHA     0xEF40000C       /* this 64 bit PCI address        */#define PCIL_PMM1LA        0xEF400010       /* Local Address                  */#define PCIL_PMM1MA        0xEF400014       /* Mask/Attribute register        */#define PCIL_PMM1PCILA     0xEF400018       /* Local address is translated to */#define PCIL_PMM1PCIHA     0xEF40001C       /* this 64 bit PCI address        */#define PCIL_PMM2LA        0xEF400020       /* Local Address                  */#define PCIL_PMM2MA        0xEF400024       /* Mask/Attribute register        */#define PCIL_PMM2PCILA     0xEF400028       /* Local address is translated to */#define PCIL_PMM2PCIHA     0xEF40002C       /* this 64 bit PCI address        *//* * Bit definitions for PMM Mask Attribute registers */#define PMM_MASK           0xFFFFF000#define PMM_MASK_4KB       0xFFFFF000#define PMM_MASK_8KB       0xFFFFE000#define PMM_MASK_16KB      0xFFFFC000#define PMM_MASK_32KB      0xFFFF8000#define PMM_MASK_64KB      0xFFFF0000#define PMM_MASK_128KB     0xFFFE0000#define PMM_MASK_256KB     0xFFFC0000#define PMM_MASK_512KB     0xFFF80000#define PMM_MASK_1MB       0xFFF00000#define PMM_MASK_2MB       0xFFE00000#define PMM_MASK_4MB       0xFFC00000#define PMM_MASK_8MB       0xFF800000#define PMM_MASK_16MB      0xFF000000#define PMM_MASK_32MB      0xFE000000#define PMM_MASK_64MB      0xFC000000#define PMM_MASK_128MB     0xF8000000#define PMM_MASK_256MB     0xF0000000#define PMM_MASK_512MB     0xE0000000#define PMM_PREFETCH       0x00000002#define PMM_ENABLE         0x00000001#define PMM_UNUSED         0x00000000/* * Register addresses for the 2 sets of 405GP PCI Target Mode (PTM) * local configuration registers.  These registers control how PCI memory * addresses are translated to Local memory addresses when the 405GP is a * PCI bus target.  PTMxLA must be set to an address that is within the * 405GP Local SDRAM Memory or ROM regions (0x00000000 - 7FFFFFFF, or * F0000000 - FFFFFFFF). */#define PCIL_PTM1MS        0xEF400030       /* Memory Size/Attribute register */#define PCIL_PTM1LA        0xEF400034       /* Local Address                  */#define PCIL_PTM2MS        0xEF400038       /* Memory Size/Attribute register */#define PCIL_PTM2LA        0xEF40003C       /* Local Address                  *//* * Bit definitions for PTM Memory Size/Attribute registers */#define PTM_SIZE           0xFFFFF000#define PTM_SIZE_4KB       0xFFFFF000#define PTM_SIZE_8KB       0xFFFFE000#define PTM_SIZE_16KB      0xFFFFC000#define PTM_SIZE_32KB      0xFFFF8000#define PTM_SIZE_64KB      0xFFFF0000#define PTM_SIZE_128KB     0xFFFE0000#define PTM_SIZE_256KB     0xFFFC0000#define PTM_SIZE_512KB     0xFFF80000#define PTM_SIZE_1MB       0xFFF00000#define PTM_SIZE_2MB       0xFFE00000#define PTM_SIZE_4MB       0xFFC00000#define PTM_SIZE_8MB       0xFF800000#define PTM_SIZE_16MB      0xFF000000#define PTM_SIZE_32MB      0xFE000000#define PTM_SIZE_64MB      0xFC000000#define PTM_SIZE_128MB     0xF8000000#define PTM_SIZE_256MB     0xF0000000#define PTM_SIZE_512MB     0xE0000000#define PTM_SIZE_1GB       0xC0000000#define PTM_SIZE_2GB       0x80000000#define PTM_ENABLE         0x00000001#define PTM_UNUSED         0x00000000/* * Bus/Device/Function used to access the PCI configuration registers * that belong to the host bridge itself (Bus = Device = Function = 0). */#define PCI_HOST_BUS        0#define PCI_HOST_DEVICE     0#define PCI_HOST_FUNCTION   0/* * 405GP-specific PCI configuration register offsets.  These are found * immediately following the architected 64 byte PCI configuration header. */#define PCI_CFG_ICS          0x44       /* PCI Interrupt Control/Status       */#define PCI_CFG_ERREN        0x48       /* Error Enable                       */#define PCI_CFG_ERRSTS       0x49       /* Error Status                       */#define PCI_CFG_BRDGOPT1     0x4A       /* Bridge Options 1                   */#define PCI_CFG_PLBBESR0     0x4C       /* PLB Slave Error Syndrome 0         */#define PCI_CFG_PLBBESR1     0x50       /* PLB Slave Error Syndrome 1         */#define PCI_CFG_PLBBEAR      0x54       /* PLB Slave Error Address            */#define PCI_CFG_CAPID        0x58       /* Capability Identifier              */#define PCI_CFG_NEXTIPTR     0x59       /* Next Item Pointer                  */#define PCI_CFG_PMC          0x5A       /* Power Management Capabilities      */#define PCI_CFG_PMCSR        0x5C       /* Power Management Control Status    */#define PCI_CFG_PMCSRBSE     0x5E       /* PMCSR PCI to PCI bridge exten      */#define PCI_CFG_DATA         0x5F       /* Data                               */#define PCI_CFG_BRDGOPT2     0x60       /* Bridge Options 2                   */#define PCI_CFG_PMSCRR       0x64       /* Power Management State Change Req. *//* * General Purpose I/O (GPIO) */#define GPIO_BASE          0xEF600700#define GPIO_OR      (GPIO_BASE+0x00)   /* GPIO Output Register               */#define GPIO_TCR     (GPIO_BASE+0x04)   /* GPIO Three-state Control Reg       */#define GPIO_ODR     (GPIO_BASE+0x18)   /* GPIO Open Drain Reg                */#define GPIO_IR      (GPIO_BASE+0x1c)   /* GPIO Input Register                *//* * Base address of Ethernet (EMAC) registers in the 405GP */#define EMAC0_BASE	0xEF600800/* * Flash / Boot ROM area */#define FLASH_START 0xFFF80000#define FLASH_END   0xFFFFFFFF/* * Header files for other cores in the 405GP */#include "405gpDcr.h"#include "uicDcr.h"            /* Universal Interrupt Controller */#include "malDcr.h"            /* Memory Access Layer DCR        */#include "sdramDcr.h"          /* SDRAM Controller               */#include "ebcDcr.h"            /* External Bus Controller        */#include "dmaDcr.h"            /* DMA Controller                 */#ifdef __cplusplus    }#endif#endif  /* INCppc405GPh */