/* romInit.s - Wind River SBC405GP ROM initialization module *//* Copyright 1984-2002 Wind River Systems, Inc. */        .data/*modification history--------------------01f,04apr02,pch  SPR 74348: Machine Check cleanup01e,18jan02,g_h  Change EBC_XXXXX macros to EBC0_XXXXX01d,10dec01,tpw  Diab-ize .reset section and rlwinm mask arguments01c,04dec01,pch  Add .reset section01b,22nov01,g_h  Add assembler abstractions (FUNC_EXPORT, FUNC_BEGIN, etc.)01a,22apr01,g_h  created from Walnut romInit.s version 01g.*//*DESCRIPTIONThis module contains the entry code for the VxWorks bootrom.The entry point romInit, is the first code executed on power-up.It sets the BOOT_COLD parameter to be passed to the genericromStart() routine.The routine sysToMonitor() jumps to the location 4 bytespast the beginning of romInit, to perform a "warm boot".This entry point allows a parameter to be passed to romStart().*/#define _ASMLANGUAGE#include "vxWorks.h"#include "sysLib.h"#include "asm.h"#include "config.h"#include "regs.h"        /* internals */        FUNC_EXPORT(romInit)  /* start of system code */        FUNC_EXPORT(_romInit) /* start of system code */        /* externals */        FUNC_IMPORT(romStart) /* system initialization routine */        _WRS_TEXT_SEG_START/***************************************************************************** romInit - entry point for VxWorks in ROM** SYNOPSIS* \ss* romInit*     (*     int startType     /@ only used by 2nd entry point @/*     )* \se*/FUNC_BEGIN(romInit)FUNC_BEGIN(_romInit)        bl      cold        bl      warm        /* copyright notice appears at beginning of ROM (in TEXT segment) */        .ascii   "Copyright 1984-2002 Wind River Systems, Inc."        .align 4cold:        li      r8, BOOT_COLD        bl      start                   /* skip over next instruction */warm:        or      r8, r3, r3              /* startType to r8 */start:        /*         * Disable external interrupts by turning off CE and EE bits in MSR	 * Also turn off Machine Check until its vector is set up.         */        mfmsr   r3                      /* r3 = msr              */        INT_MASK (r3, r4)               /* mask EE and CE bit    */	rlwinm	r4, r4, 0, 20, 18	/* turn off _PPC_MSR_ME  */        mtmsr   r4                      /* msr = r4              */        isync        /*         * Initalize registers that need to be set to zero.         */        addi    r4,r0,0x0000        mtspr   ICCR,r4                 /* turn off I-cache (warm)       */        mtspr   DCCR,r4                 /* turn off D-cache (warm)       */        mtspr   DCWR,r4                 /* all memory regions write-back */        mtspr   ESR, r4                 /* clear error status            */        mtspr   TCR, r4                 /* disable all timers            */        mtspr   PIT, r4                 /* clear the PIT timer           */        mtdcr   UIC_ER, r4              /* disable ints at the UIC       */        mtspr   XER, r4                 /* clear integer exception reg   */        mtdcr   DMA_CR0, r4             /* stop DMA channels             */        mtdcr   DMA_CR1, r4        mtdcr   DMA_CR2, r4        mtdcr   DMA_CR3, r4        /*         * Initalize registers that need to be cleared with 0xFFFFFFFF         */        addis   r4,r0,0xffff        ori     r4,r4,0xffff        mtspr   TSR, r4                 /* clear timer status            */        mtspr   DBSR, r4                /* clear debug status reg        */        mtdcr   DMA_SR, r4              /* clear DMA status reg          */        mtdcr   UIC_SR, r4              /* clear all pending UIC ints    */        /*         * Set storage guarded attribute         *     Unguarded: 0x00000000 - 0x7FFFFFFF  SDRAM         *       Guarded: 0x80000000 - 0xF7FFFFFF  PCI Memory, I/O, config,         *                                         405GP internal peripherals,         *                                         SBC405GP external peripherals         *     Unguarded: 0xF8000000 - 0xFFFFFFFF  Bootrom         */        addi    r4,r0,0x0000        ori     r4,r4,0xfffe        mtspr   SGR,r4        /*         * Invalidate the entire instruction cache. This can be done         * with a single iccci instruction in the 405 processor core.         */        iccci   r0, r0        /*         * Invalidate the entire data cache.         * The 405 processor core in the 405GP has 128 congruence classes.         * Each cache line in the 405 processor is 32 bytes.         */        li      r3, 0                         /* clear r3 */        li      r4, _DCACHE_LINE_NUM_405GP    /* load number of cache lines */        mtctr   r4rom405Dcci:        dccci   r0, r3        addi    r3, r3, _CACHE_ALIGN_SIZE     /* bump to next line */        bdnz    rom405Dcci                    /* go to invalidate */        /*         * Turn the instruction cache on for faster boot-up.         * Also, the icache is needed to help initialize Bank 0         * of the EBC to speed up accesses to flash.         * address space 0x00000000-0x07ffffff is cached         * address space 0xf8000000-0xffffffff is cached         */        lis     r3, HIADJ(_PPC405_ICCR_DEFAULT_VAL)        addi    r3, r3, LO(_PPC405_ICCR_DEFAULT_VAL)        mtspr   ICCR, r3        isync        /*         * Initialize External Bus Controller (EBC) for SBC405GP peripherals         */        bl      extBusCntlrInit        /*         * Now that the EBC Bank 0 has been set up, turn the I-cache off if         * i-cache was not specified in config.h.  It is also invalidated         * again.         */#ifndef USER_I_CACHE_ENABLE        li      r3, 0                     /* clear r3 */        mtspr   ICCR, r3                  /* turn off i-cache */        isync        iccci   r0, r0                    /* invalidate the I-cache again */#endif        /*         * Configure the SDRAM controller only if this is a cold boot.         * If the SDRAM controller is reinitialized on a warm boot, the         * boot line will get wiped out because of the ECC SDRAM memory         * initialization.         */        li      r3, BOOT_COLD        and.    r3, r3, r8             /* r8 is saved at the entry of romInit */        beq     skip        bl      sdramInitskip:        /*         * Clear the CPU reservation bit         */        li      r0, 0        lwarx   r3, r0, r0        stwcx.  r3, r0, r0        /* Initialize the stack pointer (r1) */        lis     sp, HIADJ(STACK_ADRS)        addi    sp, sp, LO(STACK_ADRS)#if     FALSE                           /* SDA not supported  */        /* initialize r2 and r13 according to EABI standard */        lis     r2, HIADJ(_SDA2_BASE_)        addi    r2, r2, LO(_SDA2_BASE_)        lis     r13, HIADJ(_SDA_BASE_)        addi    r13, r13, LO(_SDA_BASE_)#endif        /* calculate C entry point: routine - entry point + ROM base */        lis     r4, HIADJ(romStart)     /* r4 = romstart */        addi    r4, r4, LO(romStart)        lis     r5, HIADJ(romInit)      /* r5 = romInit */        addi    r5, r5, LO(romInit)        lis     r6, HIADJ(ROM_TEXT_ADRS) /* r6 = ROM_TEXT_ADRS */        addi    r6, r6, LO(ROM_TEXT_ADRS)        subf    r4, r5, r4              /* r4 = r4 - r5 */        add     r4, r4, r6              /* r4 = r4 + r6 */        mtlr    r4                      /* link register = C entry point */        or      r3, r8, r8              /* r3 = startType */        addi    sp, sp, -FRAMEBASESZ    /* get frame stack */        blr                             /* branch to link register */FUNC_END(_romInit)FUNC_END(romInit)/********************************************************************************* extBusCntlrInit - Initializes the 405GP External Bus Controller peripheral*                   bank registers for the SBC405GP board.**                   IMPORTANT: This code must run from the I-cache since the*                   peripheral bank timing register EBC_B0AP cannot be reliably*                   changed while code is being executed from bank 0.**                       Bank 0 - Flash/SRAM*                       Bank 1 - NVRAM/RTC