*                       Bank 2 - *                       Bank 3 - *                       Bank 4 - *                       Bank 5 - *                       Bank 6 - *                       Bank 7 - ** SYNOPSIS* \ss* void extBusCntlrInit*     (*     void*     )* \se** RETURNS: N/A*/FUNC_BEGIN(extBusCntlrInit)        mflr    r4                     /* save link register                  */        bl      ..getAddr..getAddr:        mflr    r3                     /* get address of ..getAddr            */        mtlr    r4                     /* restore link register value         */        addi    r4,0,10                /* set ctr to 10; used to prefetch     */        mtctr   r4                     /* 10 cache lines to fit this function */                                       /* in cache (8x10=80 instructions)     */..ebcloop:        icbt    r0,r3                  /* prefetch cache line for addr in r3  */        addi    r3,r3,32               /* move to next cache line             */        bdnz    ..ebcloop              /* continue for 10 cache lines         */        /*         * Delay to ensure all accesses to ROM are complete before changing         * bank 0 timings. 200usec should be enough.         *  200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles         */        addis   r3,0,0x0        ori     r3,r3,0xA000          /* wait 200usec have passed since reset */        mtctr   r3..spinlp:        bdnz    ..spinlp              /* spin loop */        /*         * Memory Bank 0 (16MB Flash) initialization         */        addi    r4,0,EBC0_B0AP        mtdcr   EBC0_CFGADDR,r4        addis   r4,0,0x0381        ori     r4,r4,0x5480        mtdcr   EBC0_CFGDATA,r4        addi    r4,0,EBC0_B0CR        mtdcr   EBC0_CFGADDR,r4        addis   r4,0,0xFF09        ori     r4,r4,0xC000        mtdcr   EBC0_CFGDATA,r4        /*         * Memory Bank 1 (Daughter CPLD) initialization         */        addi    r4,0,EBC0_B1AP        mtdcr   EBC0_CFGADDR,r4        addis   r4,0,0x0281        ori     r4,r4,0x5480        mtdcr   EBC0_CFGDATA,r4        addi    r4,0,EBC0_B1CR        mtdcr   EBC0_CFGADDR,r4        addis   r4,0,0xF001        ori     r4,r4,0x8000        mtdcr   EBC0_CFGDATA,r4#ifdef  INCLUDE_WR_FPGA_CARD#ifdef  WR_FPGA_CARD_ON_LOCAL_BUS        /*         * Memory Bank 2 (Wind River FPGA card "Proteus") initialization         */        addi    r4,0,EBC0_B2AP        mtdcr   EBC0_CFGADDR,r4        addis   r4,0,0x0481        ori     r4,r4,0x5A80        mtdcr   EBC0_CFGDATA,r4        addi    r4,0,EBC0_B2CR        mtdcr   EBC0_CFGADDR,r4        addis   r4,0,0x700F        ori     r4,r4,0xC000        mtdcr   EBC0_CFGDATA,r4        /*         * Memory Bank 3 (Control EPLD) initialization         */        addi    r4,0,EBC0_B3AP        mtdcr   EBC0_CFGADDR,r4        addis   r4,0,0x0181        ori     r4,r4,0x5280        mtdcr   EBC0_CFGDATA,r4        addi    r4,0,EBC0_B3CR        mtdcr   EBC0_CFGADDR,r4        addis   r4,0,0xF011        ori     r4,r4,0x8000        mtdcr   EBC0_CFGDATA,r4#endif  /* WR_FPGA_CARD_ON_LOCAL_BUS */#endif  /* INCLUDE_WR_FPGA_CARD */        /*         * Memory Bank 4 (MailBox) initialization         */        addi    r4,0,EBC0_B4AP        mtdcr   EBC0_CFGADDR,r4        addis   r4,0,0x0000        ori     r4,r4,0x0080        mtdcr   EBC0_CFGDATA,r4        addi    r4,0,EBC0_B4CR        mtdcr   EBC0_CFGADDR,r4        addis   r4,0,0xF021        ori     r4,r4,0x8000        mtdcr   EBC0_CFGDATA,r4        blrFUNC_END(extBusCntlrInit)/***************************************************************************** sdramInit -       Initializes the 405GP SDRAM controller*                   Configures SDRAM memory banks.** SYNOPSIS* \ss* void sdramInit*     (*     void*     )* \se** RETURNS: N/A*/FUNC_BEGIN(sdramInit)        mflr    r31        /*         * Fixed 32MB SDRAM configuration.         */        /*         * Set SDRAM_B0CR for bank 0. (0-32MB) Address Mode 4         */        addi    r4,0,SDRAM_B0CR        mtdcr   SDRAM_CFGADDR,r4        addis   r4,0,0x0006        ori     r4,r4,0x2001        mtdcr   SDRAM_CFGDATA,r4        /*         * Set SDRAM_B1CR for bank 1 disable         */        addi    r4,0,SDRAM_B1CR        mtdcr   SDRAM_CFGADDR,r4        addis   r4,0,0x0000        ori     r4,r4,0x0000        mtdcr   SDRAM_CFGDATA,r4        /*         * Set SDRAM_B2CR for bank 2. (32MB-64MB) Address Mode 4         */        addi    r4,0,SDRAM_B2CR        mtdcr   SDRAM_CFGADDR,r4        addis   r4,0,0x0206        ori     r4,r4,0x2001        mtdcr   SDRAM_CFGDATA,r4        /*         * Set SDRAM_B3CR for bank 3 disable         */        addi    r4,0,SDRAM_B3CR        mtdcr   SDRAM_CFGADDR,r4        addis   r4,0,0x0000        ori     r4,r4,0x0000        mtdcr   SDRAM_CFGDATA,r4        /*         * Take defaults for SDRAM Timing reg (SDRAM_TR)         */        /*         * Delay to ensure 200usec have elapsed since reset. Assume worst         * case that the core is running 200Mhz:         *   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles         */        addis   r3,0,0x0000        ori     r3,r3,0xA000        /* ensure 200usec have passed since reset */        mtctr   r3..spinlp2:        bdnz    ..spinlp2           /* spin loop */        /*         * Set memory controller options reg, SDRAM_CFG.         * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst         * read/prefetch.         */        addi    r4,0,SDRAM_CFG        mtdcr   SDRAM_CFGADDR,r4        addis   r4,0,0x8080         /* set DC_EN=1 */        ori     r4,r4,0000        mtdcr   SDRAM_CFGDATA,r4        /*         * Delay to ensure 10msec have elapsed since reset. This is         * required for the MPC952 to stabilize. Assume worst         * case that the core is running 200Mhz:         * 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles         * This delay should occur before accessing SDRAM.         */        addis   r3,0,0x001E        ori     r3,r3,0x8480        /* ensure 10msec have passed since reset  */        mtctr   r3..spinlp3:        bdnz    ..spinlp3           /* spin loop */        mtlr    r31        blr        /*         * R3 = Failing addrress         * R4 = Expected value         * R7 = Actual value         */..whups:        b       ..whupsFUNC_END(sdramInit)/***************************************************************************** resetVector - hardware reset vector** At power-on, the PPC440 starts executing at ROM address 0xfffffffc -- the* top of the address space -- which must be a jump to the reset entry point.* This jump instruction is defined as a separate .section to assist the* linker in placing it properly in the ROM.**/#if   defined(_GNU_TOOL)	.section .reset, "ax", @progbits#elif defined(_DIAB_TOOL)	.section .reset, 4, "rx"#else#error "Please add a correctly spelled .section directive for your toolchain."#endifFUNC_BEGIN(resetVector)	b	romInitFUNC_END(resetVector)