/* Structure to keep track of TX descriptor queue information */typedef struct    {    MAL_BD *    pTxDesc;                /* First descriptor in the TX ring    */    int         numTxD;                 /* Number of TX descriptors           */    int         indexTxD;               /* Current TX descriptor index        */    int         indexTxDClean;          /* Current TX cleanup descriptor index*/    UINT        getNewPacketTX;         /* Write to EMAC_TMR0 to kick off TX  */    EMAC_FREE   txFree[EMAC_TXD_MAX];   /* array of info for TX free cleanup  */    } TX_INFO;/* Flags used by the txFree arrays */#define EMAC_TX_FREE_NONE        0#define EMAC_TX_FREE_CLUSTER     1#define EMAC_TX_FREE_MBLK        2#define EMAC_TX_FREE_MBLK_LAST   3/* * The definition of the overall driver control structure.  Each instance of * the driver creates its own copy of this structure. */typedef struct ibmEmacDevice    {    END_OBJ     end;                    /* END_OBJ for this device            */    int         unit;                   /* Unit number of this EMAC device    */    UINT        baseAdrs;               /* Base address of EMAC registers     */    UINT8       enetAddr[6];            /* Ethernet MAC address               */    int         txChn0MalChannel;       /* MAL channel # for EMAC TX channel 0*/    int         txChn1MalChannel;       /* MAL channel # for EMAC TX channel 1*/    int         rxChn0MalChannel;       /* MAL channel # for EMAC RX channel 0*/    MAL_DATA *  pMalData;               /* ptr to MAL data for this EMAC      */    int         numTxChannels;          /* using 1 or 2 TX Channels           */    int         txChannel;              /* TX channel next for next transmit  */    TX_INFO     txInfo[2];              /* Tx desc info, one for each channel */    MAL_BD *    pRxDesc;                /* First descriptor in the RX ring    */    int         numRxD;                 /* Number of RX descriptors           */    int         indexRxD;               /* Current RX descriptor index        */    int         ivec;                   /* Ethernet Interrupt vector          */    int         ilevel;                 /* Ethernet Interrupt level           */    int         phyAdrs;                /* Address of PHY to be used          */    USHORT      phyAnlpar;              /* Results of auto-negotiation        */    char *      memInputAdrs;           /* Memory address from input string   */    char *      memAdrsMalloc;          /* Memory that was malloced           */    int         memSizeMalloc;          /* Size of memory that was malloced   */    char *      memAdrs;                /* Actual address to be used          */    int         memInputSize;           /* Memory size from input string      */    int         memSize;                /* Actual memory size to be used      */    UINT        inputFlags;             /* Flags passed in load string        */    UINT        localFlags;             /* Local status flags                 */    CACHE_FUNCS cacheFuncs;             /* Cache function pointers            */    CL_POOL_ID  pClPoolId;              /* Cluster pool Id                    */    M_CL_CONFIG mClCfg;                 /* mBlk & cluster config structure    */    CL_DESC     clDesc;                 /* Cluster descriptor table           */    END_ERR     lastError;              /* Last error sent to muxError        */    UINT        errorEmac;              /* saves last EMAC error              */    int         intErrorTX;             /* number of TX error interrupts      */    int         intErrorRX;             /* number of RX error interrupts      */    int         cacheLineSize;          /* size of the processor cache line   */    int         opbSpeedMhz;            /* OPB bus speed in MHz               */    UINT        stacrOpbSpeed;          /* used in STACR reg OPB speed field  */    WDOG_ID	wdRestart;		/* WD to unblock MUX in case ot fails */    } EMAC_DRV_CTRL;/* * Ethernet Register and Register Bit Definitions * The base address of the EMAC is one of the load string parameters. */#define EMAC_MR0         0x00                      /* Mode Reg 0              */#define EMAC_MR1         0x04                      /* Mode Reg 1              */#define EMAC_TMR0        0x08                      /* Transmit Mode 0         */#define EMAC_TMR1        0x0C                      /* Transmit Mode 1         */#define EMAC_RMR         0x10                      /* Receive Mode            */#define EMAC_ISR         0x14                      /* Interrupt Status        */#define EMAC_ISER        0x18                      /* Interrupt Status Enable */#define EMAC_IAHR        0x1C                      /* Individual Adrs High    */#define EMAC_IALR        0x20                      /* Individual Adrs Low     */#define EMAC_VTPID       0x24                      /* VLAN TPID Reg           */#define EMAC_VTCI        0x28                      /* VLAN TCI Reg            */#define EMAC_PTR         0x2C                      /* Pause Timer             */#define EMAC_IAHT1       0x30                      /* Ind Adrs Hash Table 1   */#define EMAC_IAHT2       0x34                      /* Ind Adrs Hash Table 2   */#define EMAC_IAHT3       0x38                      /* Ind Adrs Hash Table 3   */#define EMAC_IAHT4       0x3C                      /* Ind Adrs Hash Table 4   */#define EMAC_GAHT1       0x40                      /* Group Adrs Hash Table 1 */#define EMAC_GAHT2       0x44                      /* Group Adrs Hash Table 2 */#define EMAC_GAHT3       0x48                      /* Group Adrs Hash Table 3 */#define EMAC_GAHT4       0x4C                      /* Group Adrs Hash Table 4 */#define EMAC_LSAH        0x50                      /* Last Source Adrs High   */#define EMAC_LSAL        0x54                      /* Last Source Adrs Low    */#define EMAC_IPGVR       0x58                      /* Inter-Frame Gap Value   */#define EMAC_STACR       0x5C                      /* STA Control             */#define EMAC_TRTR        0x60                      /* TX Request Threshold    */#define EMAC_RWMR        0x64                      /* RX High/Low Water Mark  */#define EMAC_OCTX        0x68                      /* MIB Octets transmitted  */#define EMAC_OCRX        0x6C                      /* MIB Octets received     *//* * EMAC Mode Reg 0 bit definitions */#define EMAC_MR0_RXI            0x80000000      /* RX MAC idle                */#define EMAC_MR0_TXI            0x40000000      /* TX MAC idle                */#define EMAC_MR0_SRST           0x20000000      /* Soft reset                 */#define EMAC_MR0_TXE            0x10000000      /* TX MAC enable              */#define EMAC_MR0_RXE            0x08000000      /* RX MAC enable              */#define EMAC_MR0_WKE            0x04000000      /* Wake up enable             */#define EMAC_MR0_BOTH_IDLE      (EMAC_MR0_RXI | EMAC_MR0_TXI)/* * EMAC Mode Reg 1 bit definitions */#define EMAC_MR1_FDE            0x80000000      /* Full Duplex enable         */#define EMAC_MR1_ILE            0x40000000      /* Internal loopback          */#define EMAC_MR1_VLE            0x20000000      /* VLAN enable                */#define EMAC_MR1_EIFC           0x10000000      /* Enable Int. Flow Control   */#define EMAC_MR1_APP            0x08000000      /* Allow pause packet         */#define EMAC_MR1_IST            0x01000000      /* Ignore SQE test            */#define EMAC_MR1_MF_10MBPS      0x00000000      /* Medium frequency = 10Mbps  */#define EMAC_MR1_MF_100MBPS     0x00400000      /* Medium frequency = 100Mbps */#define EMAC_MR1_RFS_4K         0x00300000      /* Receive FIF0 = 4KB         */#define EMAC_MR1_TFS_2K         0x00080000      /* Transmit FIFO = 2KB        */#define EMAC_MR1_TR0_SINGLE     0x00000000      /* TX 0 single packet mode    */#define EMAC_MR1_TR0_DEPEND     0x00010000      /* TX 0 multi packet mode     */#define EMAC_MR1_TR0_MULTI      0x00008000      /* TX 0 dependent mode        */#define EMAC_MR1_TR1_SINGLE     0x00000000      /* TX 1 single packet mode    */#define EMAC_MR1_TR1_DEPEND     0x00004000      /* TX 1 multi packet mode     */#define EMAC_MR1_TR1_MULTI      0x00002000      /* TX 1 dependent mode        *//* * EMAC Transmit Mode Register 0 bit definitions */#define EMAC_TMR0_GNP0          0x80000000     /* TX 0 get new packet         */#define EMAC_TMR0_GNP1          0x40000000     /* TX 1 get new packet         */#define EMAC_TMR0_GNPD          0x20000000     /* TX dependent get new packet */#define EMAC_TMR0_FC            0x10000000     /* First channel               *//* * EMAC Receive Mode Register bit definitions */#define EMAC_RMR_SP             0x80000000     /* Strip padding               */#define EMAC_RMR_SFCS           0x40000000     /* Strip FCS                   */#define EMAC_RMR_RRP            0x20000000     /* RX runt packets             */#define EMAC_RMR_RFP            0x10000000     /* RX packets with FCS error   */#define EMAC_RMR_ROP            0x08000000     /* RX oversize packets         */#define EMAC_RMR_RPIR           0x04000000     /* RX packets w/ inrange error */#define EMAC_RMR_PPP            0x02000000     /* Propagate pause packets     */#define EMAC_RMR_PME            0x01000000     /* Promiscuous mode enable     */#define EMAC_RMR_PMME           0x00800000     /* Promiscuous multicast mode  */#define EMAC_RMR_IAE            0x00400000     /* Individual address enable   */#define EMAC_RMR_MIAE           0x00200000     /* Multiple individual address */#define EMAC_RMR_BAE            0x00100000     /* Broadcast address enable    */#define EMAC_RMR_MAE            0x00080000     /* Multicast address enable    *//* * EMAC Interrupt Status & Enable registers bit definitions *//* RX bits */#define EMAC_ISR_OVR            0x02000000     /* Overrun error               */#define EMAC_ISR_PP             0x01000000     /* Pause packet received       */#define EMAC_ISR_BP             0x00800000     /* Bad packet                  */#define EMAC_ISR_RP             0x00400000     /* Runt packet                 */#define EMAC_ISR_SE             0x00200000     /* Short event                 */#define EMAC_ISR_SYE            0x00100000     /* Symbol error                */#define EMAC_ISR_BFCS           0x00080000     /* Bad FCS                     */#define EMAC_ISR_PTLE           0x00040000     /* Packet too long             */#define EMAC_ISR_ORE            0x00020000     /* Out of range error          */#define EMAC_ISR_IRE            0x00010000     /* In range error              *//* TX bits */#define EMAC_ISR_DBDM           0x00000200     /* Dead bit TX dependent mode  */#define EMAC_ISR_DB0            0x00000100     /* Dead bit TX channel 0       */#define EMAC_ISR_SE0            0x00000080     /* SQE error TX channel 0      */#define EMAC_ISR_TE0            0x00000040     /* TX error channel 0          */#define EMAC_ISR_DB1            0x00000020     /* Dead bit TX channel 1       */#define EMAC_ISR_SE1            0x00000010     /* SQE error TX channel 1      */#define EMAC_ISR_TE1            0x00000008     /* TX error channel 1          */#define EMAC_ISR_MOS            0x00000002     /* MMA operation succeeded     */#define EMAC_ISR_MOF            0x00000001     /* MMA operation failed        */#define EMAC_ISR_NO_INTS        0x00000000     /* No interrupts               *//* The set of bits above we want to cause an Ethernet interrupt for RX error */#define EMAC_ISR_RX_INTS    0/* The set of bits above we want to cause an Ethernet interrupt for TX error */#define EMAC_ISR_TX_INTS    0/* * EMAC MII station management unit (STA Control) register bit definitions */#define EMAC_STACR_OC           0x00008000     /* Operation complete          */#define EMAC_STACR_PHYE         0x00004000     /* PHY error                   */#define EMAC_STACR_WRITE        0x00002000     /* STA command WRITE           */#define EMAC_STACR_READ         0x00001000     /* STA command READ            */#define EMAC_STACR_CLK_50MHZ    0x00000000     /* OPB bus clock freq 50MHz    */#define EMAC_STACR_CLK_83MHZ    0x00000800     /* OPB bus clock freq 83MHz    */#define EMAC_STACR_CLK_66MHZ    0x00000400     /* OPB bus clock freq 66MHz    */#define EMAC_STACR_CLK_100MHZ   0x00000C00     /* OPB bus clock freq 100MHz   *//* * EMAC Transmit Request Threshold Register bit definitions */#define EMAC_TRTR_64            0x00000000#define EMAC_TRTR_128           0x08000000#define EMAC_TRTR_192           0x10000000#define EMAC_TRTR_256           0x18000000#if defined(__STDC__) || defined(__cplusplus)IMPORT END_OBJ * ibmEmacEndLoad(char * initString);IMPORT STATUS    ibmEmacInitParse(EMAC_DRV_CTRL * pDrvCtrl, char * initString);#elseIMPORT END_OBJ * ibmEmacEndLoad ();IMPORT STATUS    ibmEmacInitParse ();#endif  /* __STDC__ */#endif  /* _ASMLANGUAGE */#ifdef __cplusplus}#endif#endif /* __INCibmEmacEndh */