/* ibmEmacEnd.c - END style IBM EMAC Ethernet driver *//*******************************************************************************   This source and object code has been made available to you by IBM on an   AS-IS basis.   IT IS PROVIDED WITHOUT WARRANTY OF ANY KIND, INCLUDING THE WARRANTIES OF   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE OR OF NONINFRINGEMENT   OF THIRD PARTY RIGHTS.  IN NO EVENT SHALL IBM OR ITS LICENSORS BE LIABLE   FOR INCIDENTAL, CONSEQUENTIAL OR PUNITIVE DAMAGES.  IBM'S OR ITS LICENSOR'S   DAMAGES FOR ANY CAUSE OF ACTION, WHETHER IN CONTRACT OR IN TORT, AT LAW OR   AT EQUITY, SHALL BE LIMITED TO A MAXIMUM OF $1,000 PER LICENSE.  No license   under IBM patents or patent applications is to be implied by the copyright   license.   Any user of this software should understand that neither IBM nor its   licensors will be responsible for any consequences resulting from the use   of this software.   Any person who transfers this source code or any derivative work must   include the IBM copyright notice, this paragraph, and the preceding two   paragraphs in the transferred software.   Any person who transfers this object code or any derivative work must   include the IBM copyright notice in the transferred software.   COPYRIGHT   I B M   CORPORATION 2000   LICENSED MATERIAL  -  PROGRAM PROPERTY OF  I B M"*******************************************************************************//*modification history--------------------02b,06dec02,jln  fix race condition on TX (SPR 83919)02a,11jul02,pch  SPRs 77845 & 78057: fix name collision with PCI drivers01z,22nov01,alr  fix (SPR 71806) ibmEmacEnd multicast join/leave exception01y,06nov01,alr  fix (SPR 71487) ibmEmacEnd: driver may instruct MUX to block		 (EMAC_TX_BLOCKED/END_ERR_BLOCK) but never call muxTxRestart01x,06nov01,alr  fix (SPR 71481/74682) ibmEmacEnd incorrectly frees mblkClChain		 when blocking / returning error to mux01w,24jan02,pch  Fix Diab warnings01v,11dec01,mcg  Modify autonegotiation wait to last only 3 seconds.01u,07nov01,pch  Fix compiler warning re "ambiguous else"01t,18oct01,mcg  Polled mode fixes, added OPB speed parameter to load string.01s,04oct01,pch  Don't call netJobAdd() if netTask is not running (SPR 70443)01r,16aug01,kab  removed second TX descriptor table; allocating memory for                 loaning buffers (SPR 68704).01q,29may01,pmr  allocating memory for buffers from cache-safe memory;                 fixed warnings.01p,10may01,mcg  extensive changes to driver to remove data cache coherency                 code, add support for both TX channels, add full-duplex flow                 control support. 405 kernel must be used.01o,09may01,pmr  removed #include "etherLib.h".  Changed ENET_HDR_REAL_SIZ to		 SIZEOF_ETHERHEADER.01n,29nov00,s_m  changes from ibm01m,20oct00,s_m  corrected inclusion of enetPhy.h01l,15nov00,mcg  give TX semaphore back if netClusterGet fails in ibmEmacSend01k,11nov00,mcg  fixed RX descriptor error interrupt handler to always call                 ibmEmacHandleRecvInt to make sure RX channel is restarted01j,28aug00,mcg  fixed multicast filter initialization for 405GP REV D.01i,05jul00,mcg  modified PHY auto-negotiation code, added full duplex support01h,07jun00,mcg  fixed EMAC_IALR setup, moved descriptor table allocation to                 malLib01g,15may00,mcg  register name updates to match 405GP User Manual01f,08may00,mcg  added RX descriptor error interrupt handler01e,17apr00,mcg  increased inter-packet gap register setting from 0x8 to 0x20.01d,21mar00,mcg  fixed cluster handling problem when bad packet is received                 added error handling01c,15feb00,mcg  added txSem2nd to fix TX problem01b,15jan00,mcg  fixed problems in initial driver startup01a,01oct99,mcg  Created*//*DESCRIPTIONThis driver is for the IBM EMAC (Ethernet Media Access Controller).  Thiscontroller is a peripheral available from the IBM Blue Logic ASIC core library.EMAC is normally part of a System on a Chip design, and it works together withanother ASIC peripheral core called the Memory Access Layer (MAL).  MAL has aseries of transmit and receive channels and its job is to DMA packet data andstatus between main memory and the EMAC (or other packet based communicationsmacros).  EMAC has two tranmsit channels and one receive channel.  Thesechannels are hardwired to channels on the MAL.  This driver works togetherwith the MAL driver (malLib).EMAC supports half-duplex and full-duplex operation for both 10Mbps and 100Mbpsdata rates.  It communctates with standard PHY devices using the MediaIndependent Interface (MII).  Chips with multiple EMACs often utilize theZMII bridge.  The ZMII bridge connects the MII interface of the EMAC(s), andallows the use of MII, RMII, or SMII physical layer devices.EMAC supports the following:        - Wake on LAN        - VLAN tagged packets        - hardware source address insertion or replacement        - Automatic FCS generation for transmitted frames        - Automatic padding of transmitted frames        - Automatic stripping of FCS and padding on received frames        - Unicast, multicast, broadcast, and promiscuous address filtering          (2 64 bit hash filters for unicast and multicast)        - Automatic retransmission of collided packets        - Programmable inter-packet gap        - Internal and external loopbackEXTERNAL SUPPORT REQUIREMENTSThis driver requires several external support functions, defined as macros:.CS    EMAC_INT_CONNECT(pDrvCtrl, routine, arg)    EMAC_INT_DISCONNECT (pDrvCtrl, routine, arg)    EMAC_INT_ENABLE(pDrvCtrl)    EMAC_INT_DISABLE(pDrvCtrl)    EMAC_REG_WRITE(pDrvCtrl, reg, data)    EMAC_REG_READ(pDrvCtrl, reg, data)    EMAC_ENET_ADDR_GET(pDrvCtrl, pAddress)    sysLanIbmEmacEnetAddrGet(pDrvCtrl, enetAdrs)    EMAC_CACHE_FLUSH(cache, adrs, bytes)    EMAC_CACHE_INVALIDATE(cache, adrs, bytes).CEThere are default values in the source code for these macros.  They presumememory mapped accesses to the device registers and the normal intConnect(),and intEnable() BSP functions.  The first argument to each is the devicecontroller structure. Thus, each has access back to all the device-specificinformation.  Having the pointer in the macro facilitates the additionof new features to this driver.The macros EMAC_INT_CONNECT, EMAC_INT_DISCONNECT, EMAC_INT_ENABLE,EMAC_INT_DISABLE, EMAC_CACHE_FLUSH, and EMAC_CACHE_INVALIDATE allow the driverto be customized for BSPs that use special versions of these routines.The macro EMAC_INT_CONNECT is used to connect the interrupt handler tothe appropriate vector.  By default it is the routine intConnect().The macro EMAC_INT_DISCONNECT is used to disconnect the interrupt handler priorto unloading the module.  By default this is a dummy routine thatreturns OK.The macro EMAC_INT_ENABLE is used to enable the interrupt level for theend device.  It is called once during initialization.  By default it is theroutine intEnable().The macro EMAC_INT_DISABLE is used to disable the interrupt level for theend device.  It is called during stop.  By default it is the routineinDisable().The macro EMAC_ENET_ADDR_GET is used get the ethernet hardware address of theof the EMAC core. This macro calls an external board level routine namelysysLanIbmEmacEnetAddrGet() to get the ethernet address.The macro EMAC_CACHE_FLUSH is used to flush a buffer (or a portion of a buffer)from the data cache to memory prior to transmitting the packet.The macro EMAC_CACHE_INVALIDATE is used to invalidate a buffer (or a portion ofa buffer) in the data cache after receiving a packet, but before handing thepacket off to the MUX layer.EXTERNAL INTERFACEBefore starting the EMAC driver,  MAL driver for the corresponding MAL shouldbe started first. The ibmEmacEnd driver provides a function ibmEmacEndLoad()that allows the caller to pass instance specific parameters to the driverwhen starting it. The instance specific parameters are passed to ibmEmacEndLoadin an ASCII string that contains tokens separated by colons.  The format of theASCII string is:   "<baseAdrs>:<malTxChn0>:<malTxChn1>:<malRxChn0>:<intVec>:<intLvl>:    <memAdrs>:<memSize>:<flags>:<phyAdrs>:<cacheLineSize>:<pMalData>:    <opbSpeedMhz>".IP <baseAdrs>The base address of the EMAC registers..IP <malTXChn0>The MAL channel number EMAC TX channel 0 is connected to..IP <malTXChn1>The MAL channel number EMAC TX channel 1 is connected to..IP <malRXChn0>The MAL channel number EMAC RX channel 0 is connected to..IP <vecNum>Ethernet Interrupt vector..IP <intLvl>Ethernet Interrupt level..IP <memAdrs>Memory address to hold buffers/clusters, or NONE (-1). If NONE, the driver willallocate memory for the buffers/clusters.  Descriptor table memory is allocatedby the MAL driver..IP <memSize>Memory size or zero..IP <flags>Driver specific flags.  Allows the customization of 3 parameters.EMAC_INPUT_TX_COPY:By default, the ibmEmacEnd driver uses a zero copy strategy whentransmitting a packet.  However, if this flag is set, the driverwill obtain a new buffer/cluster and copy the packet data fromthe mBlk into the new buffer before transmitting the packet.EMAC_INPUT_UNCACHED_BUF:If the ibmEmacDriver allocates its own memory for buffers/clusters, itby default allocates cached memory and then manages the data cachecoherency when transmitting (flush) and receiving (invalidate) packets.However, if this flags is set, the driver will allocate cache-safememory for buffer/clusters. NOTE: if the EMAC_INPUT_UNCACHED_BUF isset, the EMAC_INPUT_TX_COPY flag must also be set.EMAC_INPUT_TX_2_CHANNEL:By default, the ibmEmacEnd driver utilizes only 1 of the 2 transmitchannels.  However, if this flags is set, the driver will use bothtransmit channels in independent mode..IP <phyAdrs>Address of the PHY device attached to MII interface of EMAC (0-31)..IP <cacheLineSize>Size of the processor data cache line..IP <pMalData>Pointer to the MAL driver control structure this EMAC is attached to.  ThemalInit() function returns a pointer to this structure..IP <opbSpeedMhz>The speed of the OPB bus in MHz.INCLUDES:end.h endLib.h etherMultiLib.h malLib.hSEE ALSO: muxLib, endLib, netBufLib, malLib*/#include "vxWorks.h"#include "wdLib.h"#include "stdlib.h"#include "taskLib.h"#include "logLib.h"#include "intLib.h"#include "netLib.h"#include "stdio.h"#include "stdlib.h"#include "sysLib.h"#include "iv.h"#include "memLib.h"#include "semLib.h"#include "cacheLib.h"#include "sys/ioctl.h"#include "enetPhy.h"#ifndef DOC#include "net/mbuf.h"#endif  /* DOC */#include "net/protosw.h"#include "sys/socket.h"#include "errno.h"#include "net/if.h"#include "net/route.h"#include "netinet/in.h"#include "netinet/in_systm.h"#include "netinet/in_var.h"#include "netinet/ip.h"#include "netinet/if_ether.h"#include "net/if_subr.h"#include "m2Lib.h"#include "etherMultiLib.h"              /* multicast stuff. */#include "end.h"                        /* Common END structures. */#include "netBufLib.h"#include "muxLib.h"#include "wdLib.h"#define END_MACROS#include "endLib.h"#include "lstLib.h"#include "ibmEmacEnd.h"#include "malLib.h"/* forward declarations, must precede the include of zmiiLib.c */IMPORT void sysPlbOutLong(ULONG address, UINT data);IMPORT UINT sysPlbInLong(ULONG address);#ifdef INCLUDE_ZMII  #include "zmiiLib.c"              /* ZMII bridge code.                      */#endif/* Cache macros */#ifndef EMAC_CACHE_INVALIDATE#define EMAC_CACHE_INVALIDATE(address, len) \        CACHE_DRV_INVALIDATE (&pDrvCtrl->cacheFuncs, (address), (len))#endif  /* EMAC_CACHE_INVALIDATE */#ifndef EMAC_CACHE_FLUSH#define EMAC_CACHE_FLUSH(address, len) \        CACHE_DRV_FLUSH (&pDrvCtrl->cacheFuncs, (address), (len))#endif  /* EMAC_CACHE_FLUSH *//* * Default macro definitions for BSP interface. * These macros can be redefined in a wrapper file, to generate * a new module with an optimized interface. */#ifndef EMAC_INT_CONNECT#define EMAC_INT_CONNECT(pDrvCtrl,routine,arg,pResult) \    { \    *pResult = (intConnect) ((VOIDFUNCPTR *)INUM_TO_IVEC (pDrvCtrl->ivec), \                             routine, (int)arg); \    }#endif /*EMAC_INT_CONNECT*/#ifndef EMAC_INT_DISCONNECTLOCAL VOID dummyISR (void) { };#define EMAC_INT_DISCONNECT(pDrvCtrl,routine,arg,pResult) \    { \    *pResult = (intConnect) ((VOIDFUNCPTR *)INUM_TO_IVEC (pDrvCtrl->ivec), \                             dummyISR, (int)arg); \    }#endif /*EMAC_INT_DISCONNECT*/#ifndef EMAC_INT_ENABLE#define EMAC_INT_ENABLE(pDrvCtrl) \    { \    intEnable(pDrvCtrl->ilevel); \    }#endif /* EMAC_INT_ENABLE*/#ifndef EMAC_INT_DISABLE#   define EMAC_INT_DISABLE(pDrvCtrl) \    { \    intDisable(pDrvCtrl->ilevel); \    }#endif#ifndef EMAC_REG_WRITE#define EMAC_REG_WRITE(pDrvCtrl,addr,value) \    { \    (sysPlbOutLong((pDrvCtrl->baseAdrs + (addr)),(value))); \    }#endif /* EMAC_REG_WRITE */#ifndef EMAC_REG_READ#define EMAC_REG_READ(pDrvCtrl,addr,data) \    { \    ((data) = (sysPlbInLong((pDrvCtrl->baseAdrs + (addr)))));  \    }#endif /* EMAC_REG_READ */#ifndef EMAC_ENET_ADDR_GET#define EMAC_ENET_ADDR_GET(pDrvCtrl, pAddress) \    { \    IMPORT STATUS sysLanIbmEmacEnetAddrGet (EMAC_DRV_CTRL *pDrvCtrl, \                                          UINT8 *enetAdrs); \    sysLanIbmEmacEnetAddrGet (pDrvCtrl, pAddress); \    }#endif /* EMAC_ENET_ADDR_GET *//* A shortcut for getting the hardware address from the MIB II stuff. */#define END_HADDR(pEnd) \                ((pEnd)->mib2Tbl.ifPhysAddress.phyAddress)#define END_HADDR_LEN(pEnd) \                ((pEnd)->mib2Tbl.ifPhysAddress.addrLength)/* externs */IMPORT int endMultiLstCnt (END_OBJ *);IMPORT int netTaskId;                           /* from netwrs/netLib.c */#ifdef DRV_DEBUG                  /* For debugging purposes. See ibmEmacEnd.h */#undef  LOCAL#define LOCALEMAC_DRV_CTRL * ibmEmacDebugPtr;int     ibmEmacDebug = (                    /* DRV_DEBUG_RX       | */                    /* DRV_DEBUG_TX       | */                    /* DRV_DEBUG_INT      | */                       DRV_DEBUG_POLL     |                       DRV_DEBUG_POLL_RX  |                       DRV_DEBUG_POLL_TX  |                    /* DRV_DEBUG_LOAD     | */                    /* DRV_DEBUG_IOCTL    | */                    /* DRV_DEBUG_RESET    | */                    /* DRV_DEBUG_MCAST    | */                       DRV_DEBUG_ERROR    |                    /* DRV_DEBUG_INFO     | */                    /* DRV_DEBUG_START    | */                    /* DRV_DEBUG_SEND     | */                    /* DRV_DEBUG_RECV     | */                       DRV_DEBUG_ENET_INT |                    /* DRV_DEBUG_STATUS   | */                    /* DRV_DEBUG_TX_CLEAN | */                       DRV_DEBUG_CFG      |                       DRV_DEBUG_PHY