/* mcpx750.h - Motorola PowerPlus board header *//* Copyright 1984-2001 Wind River Systems, Inc. *//* Copyright 1996,1997,1998,1999 Motorola, Inc. All Rights Reserved *//*modification history--------------------01u,25mar02,mil  Changed FLOPPY_INT_ macros to FD_INT_. (SPR #68689)01t,16sep01,dat  Use of WRS_ASM macro01s,01may00,rcs  removed                 PCI_ID_VEND_DEC21554,PCI_ID_DEV_DEC21554,PCI_ID_BR_DEC2155401r,15dec99,rhv  Adding support for non-MCPN750 cPCI boards.01q,07sep99,tm   Added missing ZCIO_DD_PORTA/B/C macros for z8536 (SPR 22830)01p,30apr99,srr  Make WR/S code review changes.01o,22feb99,scb  Moved PCI2DRAM_BASE_ADRS out of "mcpx750.h" and into "config.h".01n,26jan99,scb  Added SYS_REG_MCR_... defines for MCPN750 256MB board.01m,18jan99,scb  Added support for END driver on dec21143.01l,11nov98,scb  Added DEC2115X_PCI_DEV_NUMBER01k,05nov98,scb  Added _SYS_SM_ANCHOR_POLLING_LIST01j,04nov98,rhv  Corrected an error in the definition of                 DEC2155X_DOORBELL11_INT_LVL.01i,23oct98,rhv  Modified ATA support to include MCPN750 and correcting errors                 in EIDE interrupt vector definitions.01h,21sep98,rhv  Added Vital Product Data support.01g,04sep98,scb  Added shared memory support (MCP750 master and mem repository)01f,28aug98,rhv  Added new defines to support processor data bus parity.01e,05aug98,rhv  Removing #ifndef's from Dec2155x defines.01d,05aug98,scb  Changed #ifndef guard to the correct name.01c,30jul98,scb  Changed CPU_PCI_MEM_ADRS to 0xc2000000.01b,29jul98,rhv  Added PCI insert routines.01a,29jul98,scb  Derived from mcp750/mv2600.h, revision 01l.*//*This file contains I/O addresses and related constants for theMotorola PowerPlus board.*/#ifndef __INCmcpx750h#define __INCmcpx750h#ifdef __cplusplusextern "C" {#endif/* ATA/EIDE support */#include "drv/pcmcia/pccardLib.h"#include "drv/hdisk/ataDrv.h"/* * Factor board features here, the CONFIGx... defines refer to * functionality related items such as ISA interrupts. */#ifdef MCP750#   define CONFIG1_MPIC_INT_TYPE	/* MPIC interrupt configuration */#   define CONFIG1_ISA_INT_TYPE 	/* ISA interrupt configuration */#   define CONFIG1_PLANAR_PCI		/* Planar PCI device configuration */#   define CONFIG1_PLANAR_ISA		/* Planar ISA device configuration */#   define CONFIG1_SYS_REG_CCR		/* System Configuration register */#   define CONFIG1_SYS_REG_MCR		/* Memory control register */#   define CONFIG1_SYS_REG_BMFR 	/* Base Module Features register */#   define CONFIG1_SYS_REG_BMEFR	/* Base Module Extended Features reg */#   define CONFIG1_SYS_REG_BMSR 	/* Base Module Status register */#   define CONFIG1_SYS_REG_SYSLED	/* System LED register */#   define CONFIG1_SYS_REG_BSR		/* Board Status register */#   define CONFIG1_SYS_REG_BLRR 	/* Board Last Reset register */#   define CONFIG1_SYS_REG_BRDFAIL_LED	/* Board Fail LED register */#endif#ifdef MCPN750#   define CONFIG2_MPIC_INT_TYPE	/* MPIC interrupt configuration */#   define CONFIG2_ISA_INT_TYPE 	/* ISA interrupt configuration */#   define CONFIG2_PLANAR_PCI		/* Planar PCI device configuration */#   define CONFIG2_PLANAR_ISA		/* Planar ISA device configuration */#   define CONFIG1_SYS_REG_CCR		/* System Configuration register */#   define CONFIG2_SYS_REG_MCR		/* Memory control register */#   define CONFIG2_SYS_REG_BMFR 	/* Base Module Features register */#   define CONFIG2_SYS_REG_BMEFR	/* Base Module Extended Features reg */#   define CONFIG1_SYS_REG_BMSR 	/* Base Module Status register */#   define CONFIG1_SYS_REG_SYSLED	/* System LED register */#   define CONFIG1_SYS_REG_BSR		/* Board Status register */#   define CONFIG2_SYS_REG_BLRR 	/* Board Last Reset register */#   define CONFIG2_SYS_REG_CPGAR	/* cPCI Geographic Address register */#   define CONFIG2_SYS_REG_PINTA	/* PINTA routing register */#   define CONFIG2_SYS_REG_ABRTBTN	/* Abort button register */#   define CONFIG2_SYS_REG_BRDFAIL_LED	/* Board Fail LED register */#endif/* Floppy disk support */#define FD_MAX_DRIVES	4#define FD_BASE_ADDR	pc87303_FDC	/* See super I/O section */#define FD_DMA_CHAN	2#ifdef	INCLUDE_FD#   ifndef	INCLUDE_DOSFS#	define	INCLUDE_DOSFS	/* file system to be used */#   endif#   ifndef	INCLUDE_ISADMA#	define	INCLUDE_ISADMA	/* uses ISA DMA driver */#   endif#   ifndef _ASMLANGUAGE	/* to stop compiler warnings */#	include "blkIo.h"	IMPORT STATUS	fdDrv (UINT, UINT);	IMPORT BLK_DEV* fdDevCreate (UINT, UINT, UINT, UINT);#   endif#endif/* Boot Line parameters are stored in the 2nd 256 byte block */#undef	NV_BOOT_OFFSET#define NV_BOOT_OFFSET		256 /* skip 1st 256 bytes */#define NV_RAM_SIZE		BBRAM_SIZE#define NV_RAM_ADRS		((char *) BBRAM_ADRS)#define NV_RAM_INTRVL		1/* PCI I/O function defines */#define INT_NUM_IRQ0		INT_VEC_IRQ0#ifndef _ASMLANGUAGE#ifndef PCI_IN_BYTE#   define PCI_IN_BYTE(x)	sysPciInByte (x)    IMPORT  UINT8		sysPciInByte  (UINT32 address);#endif#ifndef PCI_IN_WORD#   define PCI_IN_WORD(x)	sysPciInWord (x)    IMPORT  UINT16		sysPciInWord  (UINT32 address);#endif#ifndef PCI_IN_LONG#   define PCI_IN_LONG(x)	sysPciInLong (x)    IMPORT  UINT32		sysPciInLong  (UINT32 address);#endif#ifndef PCI_OUT_BYTE#   define PCI_OUT_BYTE(x,y)	sysPciOutByte (x,y)    IMPORT  void		sysPciOutByte (UINT32 address, UINT8  data);#endif#ifndef PCI_OUT_WORD#   define PCI_OUT_WORD(x,y)   sysPciOutWord (x,y)    IMPORT  void	       sysPciOutWord (UINT32 address, UINT16 data);#endif#ifndef PCI_OUT_LONG#   define PCI_OUT_LONG(x,y)	sysPciOutLong (x,y)    IMPORT  void		sysPciOutLong (UINT32 address, UINT32 data);#endif#ifndef PCI_INSERT_LONG#   define PCI_INSERT_LONG(a,m,d) sysPciInsertLong((a),(m),(d))    IMPORT  void                  sysPciInsertLong(UINT32 adrs, UINT32 mask, \                                                   UINT32 data);#endif#ifndef PCI_INSERT_WORD#   define PCI_INSERT_WORD(a,m,d) sysPciInsertWord((a),(m),(d))    IMPORT  void                  sysPciInsertWord(UINT32 adrs, UINT16 mask, \                                                   UINT16 data);#endif#ifndef PCI_INSERT_BYTE#   define PCI_INSERT_BYTE(a,m,d) sysPciInsertByte((a),(m),(d))    IMPORT  void                  sysPciInsertByte(UINT32 adrs, UINT8 mask, \                                                   UINT8 data);#endif#endif	/* _ASMLANGUAGE *//* Cache Line Size - 8 32-bit value = 64 bytes */#define PCI_CLINE_SZ		0x8/* Latency Timer value - 255 PCI clocks */#define PCI_LAT_TIMER		0xff/* clock rates *//* Calculate Memory Bus Rate in Hertz */#define MEMORY_BUS_SPEED	( sysGetBusSpd() * 1000000)/* System clock (decrementer counter) frequency determination */#define DEC_CLOCK_FREQ		((sysGetBusSpd()==67)?66666666:33333333)/* CIO clocks and stuff */#define CIO_RESET_DELAY 	5000#define ZCIO_HZ 		2500000 /* 2.5 MHz clock */#define CIO_INT_VEC		9#define Z8536_TC		ZCIO_HZ/* * The PowerPC Decrementer is used as the system clock. * It is always included in this BSP.  The following defines * are used by the system clock library. */#define SYS_CLK_RATE_MIN	10		/* minimum system clock rate */#define SYS_CLK_RATE_MAX	5000		/* maximum system clock rate *//* * This macro returns the positive difference between two unsigned ints. * Useful for determining delta between two successive decrementer reads. */#define DELTA(a,b)		( abs((int)a - (int)b) )/* * Auxiliary Clock support is an optional feature that is not supported * by all BSPs.  The following defines are used by the aux clock library. */#define AUX_CLK_RATE_MIN	40		/* min auxiliary clock */#define AUX_CLK_RATE_MAX	5000		/* max auxiliary clock rate *//* Common I/O synchronizing instructions */#ifndef EIEIO_SYNC#   define EIEIO_SYNC  _WRS_ASM (" eieio; sync")#endif	/* EIEIO_SYNC */#ifndef EIEIO#   define EIEIO    _WRS_ASM (" eieio")#endif	/* EIEIO *//*  * The following macros define access to PCI and ISA space from the CPU * and the base addresses of PCI and ISA spaces on the bus. * These macros contain the correct starting addresses and sizes * for use in the BSP and user programming. *//* Legacy ISA space size. */#define ISA_LEGACY_SIZE 0x00004000/* Access to PCI ISA I/O space */#define ISA_MSTR_IO_LOCAL   	0x80000000#define ISA_MSTR_IO_BUS     	0x00000000	/* 0 based addressing */#define ISA_MSTR_IO_SIZE 	0x00010000	/* 64 kbytes *//* Access to PCI I/O space */#define PCI_MSTR_IO_LOCAL	(ISA_MSTR_IO_LOCAL + ISA_MSTR_IO_SIZE)#define PCI_MSTR_IO_BUS		(ISA_MSTR_IO_BUS   + ISA_MSTR_IO_SIZE)#define PCI_MSTR_IO_SIZE	0x00800000	/* 8MB *//* * Access to PCI nonprefetchable memory space (including ISA memory space) * Note the size PCIMSTR_MEMIO_SIZE is defined in config.h */#define PCI_MSTR_MEMIO_LOCAL	0xc0000000#define PCI_MSTR_MEMIO_BUS	0x00000000	/* 0 based addressing */#define PCI_MSTR_MEMIO_1MB_OFF	0x00100000	/* Offset:PCI 1MB memory space*//* Access to PCI memory space (size defined in config.h) */#define PCI_MSTR_MEM_LOCAL	(PCI_MSTR_MEMIO_LOCAL + PCI_MSTR_MEMIO_SIZE)#define PCI_MSTR_MEM_BUS	(PCI_MSTR_MEMIO_BUS   + PCI_MSTR_MEMIO_SIZE)/* PCI Access to local memory space */#define PCI_SLV_MEM_LOCAL	LOCAL_MEM_LOCAL_ADRS#define PCI_SLV_MEM_BUS		0x80000000#define PCI_SLV_MEM_SIZE	DRAM_SIZE/* setup the dynamic PCI memory space for PReP */#define PCI_DYNAMIC_MEM_LOCAL (PCI_MSTR_MEM_LOCAL + 0x0)#define PCI_DYNAMIC_MEM_BUS   (PCI_MSTR_MEM_BUS + 0x0)#define PCI2DRAM_BASE_ADRS	PCI_SLV_MEM_BUS	 /* needed for usrNetwork.c *//* * PCI MASTER MEMORY WINDOW LIMITS * * These values are strictly defined by the base memory addresses and window * sizes of the spaces defined above.  These values must be correct for the * sysBusProbe() memory range checks for the PCI bus to work properly. */#define PCI_MSTR_LO_ADRS	(ISA_MSTR_IO_LOCAL)#define PCI_MSTR_HI_ADRS	(PCI_MSTR_MEM_LOCAL + PCI_MSTR_MEM_SIZE)/* Base address of HW devices as seen from CPU */#define FALCON_BASE_ADRS	0xfef80000#define FALCON_REG_SIZE 	0x00010000#define FALCON_BASE_UPPER_ADRS	(FALCON_BASE_ADRS>>16)#define FALCON_DRAM_ATTR	0xfef80010#define FALCON_RESET_STAT_U	0xfef80400#define FALCON_REV_ID		0xfef80009#define RAVEN_BASE_ADRS 	0xfeff0000#define RAVEN_REG_SIZE		0x00010000#define FLASH_BASE_ADRS 	0xFF000000#define FLASH_MEM_SIZE		0x01000000/* MPIC configuration defines */#define MPIC_BASE_ADRS		0xfc000000#define MPIC_REG_SIZE		0x00040000#define MPIC_PCI_BASE_ADRS	( MPIC_BASE_ADRS - PCI_MSTR_MEMIO_LOCAL )/* memory map as seen on the PCI bus */#define PCI_CNFG_ADRS		0x00800000	/* base of PCI config space */#define PCI_IO_ADRS		0x01000000	/* base of PCI I/O address */#define PCI_MEM_ADRS		0x01000000	/* base of PCI MEM address *//* * Primary PCI bus configuration space address and data register addresses * as seen by the CPU on the local bus. */#define PCI_PRIMARY_CAR 	0x80000CF8 /* PCI config address register */#define PCI_PRIMARY_CDR 	0x80000CFC /* PCI config data	 register *//* * PCI Config Space device addresses based on their device number * * Bit 32 is set to enable CONFIG_DATA accesses to PCI Cycles */#define CNFG_START_SEARCH	0x5800	   /* PCI Space starting offset */#define CNFG_RAVEN_ADRS 	ISA_MSTR_IO_LOCAL /* Raven PCI and MPIC ASIC*/#define CNFG_IBC_ADRS		0x80005800 /* IBC */#define CNFG_SCSI_ADRS		0x80006000 /* SCSI */#define CNFG_VGA_ADRS		0x80007800 /* Graphics Device */#define CNFG_PMC1_ADRS		0x80008000 /* PMC Slot1 */#define CNFG_SCSI2_ADRS 	0x80008800 /* Secondary SCSI */#define CNFG_PMC2_ADRS		0x80009800 /* PMC Slot 2 or PCIX *//* Number of PCI devices */#define NUM_PCI_DEVS		4/* PCI Device/Vendor IDs */#ifdef CONFIG1_PLANAR_PCI#   define PCI_ID_PRI_LAN	PCI_ID_LN_DEC21140 /* Id for Primary LAN */#   define PCI_ID_IBC		0x05861106	/* Id for VT82586 PBC */#   define PCI_ID_IDE		0x05711106	/* Id for VT82586 IDE */#   define DEC2115X_PCI_DEV_NUMBER 0x14         /* Dec 21154 dev number */#endif#ifdef CONFIG2_PLANAR_PCI#   define PCI_ID_PRI_LAN	PCI_ID_LN_DEC21143 /* Id for Primary LAN */#   define PCI_ID_IBC		0x05861106	/* Id for VT82586 PBC */#   define PCI_ID_IDE		0x05711106	/* Id for VT82586 IDE */#endif#define PCI_ID_RAVEN		0x48011057	/* Id for RAVEN ASIC */#define PCI_ID_LN_DEC21140	0x00091011	/* Id DEC chip 21140 */#define PCI_ID_LN_DEC21143	0x00191011	/* Id DEC chip 21143 */#define PCI_ID_LN_DEC21040	0x00021011	/* Id DEC chip 21040 */#define PCI_ID_BR_DEC21150	0x00221011	/* Id DEC 21150 PCI bridge */#define PCI_ID_SEC_LAN		PCI_ID_LN_DEC21040 /* Id for Secondary LAN */#define PCI_ID_NCR810		0x00011000	/* Id for SYM53C810A Chip */#define PCI_ID_NCR825		0x00031000	/* Id for SYM53C825 Chip */#define PCI_ID_NCR860		0x00061000	/* Id for SYM53C860 Chip */#define PCI_ID_NCR875		0x000f1000	/* Id for SYM53C875 Chip */#define PCI_ID_SCSI		PCI_ID_NCR825	/* Id for Primary SCSI */#define PCI_ID_SEC_SCSI 	PCI_ID_NCR825	/* Id for Secondary SCSI */#define PCI_ID_5434		0x00a81013	/* Id for CL-GD534 chip */#define PCI_ID_5436		0x00ac1013	/* Id for CL-GD536 chip */#define PCI_ID_USB		0x30381106	/* USB (function 2 of PBC) */#define PCI_ID_PM		0x30401106	/* Power Mgmt (func 3 of PBC) *//* Special dec21143 configuration device driver area register */#define PCI_CFG_21143_DA	0x40/* Base address register defines */#define PCI_BASEADDR_IO           (1<<0) /* PCI I/O space */#define PCI_BASEADDR_MEM	  (0<<0) /* PCI Memory space */#define PCI_BASEADDR_MEM_TYPE     (3<<1) /* memory type mask */#define PCI_BASEADDR_MEM_32BIT    (0<<1) /* map anywhere in 32-bit addr space */#define PCI_BASEADDR_MEM_ONEMEG   (1<<1) /* map below 1MB */#define PCI_BASEADDR_MEM_64BIT    (2<<1) /* map anywhere in 64-bit addr space */#define PCI_BASEADDR_MEM_PREFETCH (1<<3) /* prefetchable *//* cmd_reg defines */#define PCI_CMDREG_IOSP      (1<<0)  /* Enable IO space accesses */#define PCI_CMDREG_MEMSP     (1<<1)  /* Enable MEM space accesses */#define PCI_CMDREG_MASTR     (1<<2)  /* Enable PCI Mastership */#define PCI_CMDREG_SPCYC     (1<<3)  /* Monitor special cycles */#define PCI_CMDREG_MEMWINV   (1<<4)  /* Enable memory write and invalidate */#define PCI_CMDREG_VGASNP    (1<<5)  /* Enable VGA palette snooping */#define PCI_CMDREG_PERR      (1<<6)  /* Enable Parity error response */#define PCI_CMDREG_STEP      (1<<7)  /* Enable address/data stepping */#define PCI_CMDREG_SERR      (1<<8)  /* Enable SERR driver */#define PCI_CMDREG_FSTB2B    (1<<9)  /* Enable back to back transactions *//* PCI Space Definitions  -- For configuring the RAVEN *//* PPC Slave Attribute bit definitions */#define CPU2PCI_ATTR_REN     (1<<7)  /* Read enable */#define CPU2PCI_ATTR_WEN     (1<<6)  /* Write enable */#define CPU2PCI_ATTR_WPEN    (1<<4)  /* Write post enable */#define CPU2PCI_ATTR_MEM     (1<<1)  /* PCI memory cycle */#define CPU2PCI_ATTR_IOM     (1<<0)  /* PCI I/O mode *//* CPU to PCI definitions */#define CPU2PCI_MSATT_MEM	( CPU2PCI_ATTR_REN | CPU2PCI_ATTR_WEN | \				  CPU2PCI_ATTR_MEM )#define CPU2PCI_MSATT_IO	( CPU2PCI_ATTR_REN | CPU2PCI_ATTR_WEN )#define CPU2PCI_MSATT_DISABLED  ( CPU2PCI_MSATT_MEM & ~( CPU2PCI_ATTR_REN | \						         CPU2PCI_ATTR_WEN ) )/* STANDARD ( PREP ) mapping of PCI space */