/* disable PCI address space 0 */#define CPU2PCI_ADDR0_START_VAL 0x0000#define CPU2PCI_ADDR0_END_VAL	0x0000#define CPU2PCI_OFFSET0_VAL	((0x0-CPU2PCI_ADDR0_START_VAL) & 0xffff)#define CPU2PCI_MSATT0_VAL	CPU2PCI_MSATT_DISABLED/* disable PCI address space 1 */#define CPU2PCI_ADDR1_START_VAL 0x0000#define CPU2PCI_ADDR1_END_VAL	0x0000#define CPU2PCI_OFFSET1_VAL	((0x0-CPU2PCI_ADDR1_START_VAL) & 0xffff)#define CPU2PCI_MSATT1_VAL	CPU2PCI_MSATT_DISABLED/* setup address space 2 for PCI MEM space */#define CPU2PCI_ADDR2_START_VAL (PCI_MSTR_MEMIO_LOCAL>>16)#define CPU2PCI_ADDR2_END_VAL	0xfcff#define CPU2PCI_OFFSET2_VAL	((0x0-CPU2PCI_ADDR2_START_VAL) & 0xffff)/* setup address space 3 for PCI I/O space */#define CPU2PCI_ADDR3_START_VAL (ISA_MSTR_IO_LOCAL>>16)#define CPU2PCI_ADDR3_END_VAL	0xbf7f#define CPU2PCI_OFFSET3_VAL	((0x0-CPU2PCI_ADDR3_START_VAL) & 0xffff)/* defines that are used in romInit.s */#define CPU2PCI_ADDR0_START	CPU2PCI_ADDR0_START_VAL#define CPU2PCI_ADDR0_END	CPU2PCI_ADDR0_END_VAL#define CPU2PCI_OFFSET0 	CPU2PCI_OFFSET0_VAL#define CPU2PCI_MSATT0		CPU2PCI_MSATT0_VAL#define CPU2PCI_ADDR1_START	CPU2PCI_ADDR1_START_VAL#define CPU2PCI_ADDR1_END	CPU2PCI_ADDR1_END_VAL#define CPU2PCI_OFFSET1 	CPU2PCI_OFFSET1_VAL#define CPU2PCI_MSATT1		CPU2PCI_MSATT1_VAL#define CPU2PCI_ADDR2_START	CPU2PCI_ADDR2_START_VAL#define CPU2PCI_ADDR2_END	CPU2PCI_ADDR2_END_VAL#define CPU2PCI_OFFSET2 	CPU2PCI_OFFSET2_VAL#define CPU2PCI_MSATT2		CPU2PCI_MSATT_MEM#define CPU2PCI_ADDR3_START	CPU2PCI_ADDR3_START_VAL#define CPU2PCI_ADDR3_END	CPU2PCI_ADDR3_END_VAL#define CPU2PCI_OFFSET3 	CPU2PCI_OFFSET3_VAL#define CPU2PCI_MSATT3		CPU2PCI_MSATT_IO/* PCI to CPU definitions */#ifdef LOCAL_MEM_AUTOSIZE#   define DRAM_SIZE		((ULONG)sysPhysMemTop() - LOCAL_MEM_LOCAL_ADRS)#else#   define DRAM_SIZE		(LOCAL_MEM_SIZE - LOCAL_MEM_LOCAL_ADRS)#endif#define PCI2CPU_ADDR0_START	(PCI_SLV_MEM_BUS & 0xffff0000)#define PCI2CPU_ADDR0_END	((PCI_SLV_MEM_BUS + PCI_SLV_MEM_SIZE \				  - 0x10001) >> 16)#define PCI2CPU_ADDR0_RANGE	(PCI2CPU_ADDR0_START | PCI2CPU_ADDR0_END)#define PCI2CPU_OFFSET0 	(((0x0-PCI_SLV_MEM_BUS)>>16) & 0x0000ffff)#define PCI2CPU_ATT0		0xf2#define PCI2CPU_ADDR1_START	((PCI_SLV_MEM_BUS + PCI_SLV_MEM_SIZE \				  - 0x10000) & 0xffff0000)#define PCI2CPU_ADDR1_END	((PCI_SLV_MEM_BUS + PCI_SLV_MEM_SIZE \				  - 0x10000) >> 16)#define PCI2CPU_ADDR1_RANGE	(PCI2CPU_ADDR1_START | PCI2CPU_ADDR1_END)#define PCI2CPU_OFFSET1 	(((0x0-PCI_SLV_MEM_BUS)>>16) & 0x0000ffff)#define PCI2CPU_ATT1		0xe2/* * Address decoders 2 and 3 are not currently used, so they are * set to point to an address that is not used on the PCI bus */#define PCI2CPU_ADDR2_RANGE	0xfff0fff0#define PCI2CPU_OFFSET2 	0x0#define PCI2CPU_ATT2		0x0#define PCI2CPU_ADDR3_RANGE	0xfff0fff0#define PCI2CPU_OFFSET3 	0x0#define PCI2CPU_ATT3		0x0/* * Allocate PCI Memory and I/O Space Offsets for PCI devices * * All devices on the primary and secondary busses are allocated 64 kb spaces. * The PMC Span can control up to four PMCs. *//* LAN_DEV_SPACE autoconfigured but still needed for clean compile */#define LAN_DEV_SPACE		0x20000#define SCSI_DEV_SPACE		0x10000/* PCI view of PCI I/O Space for PCI devices */#define PCI_IO_SCSI_ADRS	(PCI_IO_ADRS + SCSI_DEV_SPACE)	/* 53C825 *//* PCI view of PCI Memory Space for PCI devices *//* Allocated base address of HW devices as seen from CPU */#define SCSI_BASE_ADRS		( PCI_MSTR_IO_LOCAL + SCSI_DEV_SPACE )/* LAN_BASE_ADRS autoconfigured but still needed for clean compile */#define LAN_BASE_ADRS		( PCI_MSTR_IO_LOCAL + LAN_DEV_SPACE )/* pc87303 ISA super IO device (ISASIO) keybrd, serial, Parallel port */#define pc87303_KBD_CTRL	(ISA_MSTR_IO_LOCAL + 0x0064)	/* keyboard */#define pc87303_INDX_REG	(ISA_MSTR_IO_LOCAL + 0x0398)	/* index reg */#define pc87303_DATA_REG	(ISA_MSTR_IO_LOCAL + 0x0399)	/* data reg */#define pc87303_PP		(ISA_MSTR_IO_LOCAL + 0x03bc)	/* parallel */#define pc87303_COM1		(ISA_MSTR_IO_LOCAL + 0x03f8)	/* serial 1 */#define pc87303_COM2		(ISA_MSTR_IO_LOCAL + 0x02f8)	/* serial 2 */#ifdef CONFIG2_PLANAR_ISA#   define pc87303_COM3 	(ISA_MSTR_IO_LOCAL + 0x03e8)	/* serial 3 */#   define pc87303_COM4 	(ISA_MSTR_IO_LOCAL + 0x02e8)	/* serial 4 */#endif#define pc87303_FDC		(ISA_MSTR_IO_LOCAL + 0x03f0)	/* floppy *//* z85230 synchronous & Asynchronous serial communications chip */#define z85230_PORTB_CTRL	(ISA_MSTR_IO_LOCAL + 0x0840)	/* serial 4 */#define z85230_PORTB_DATA	(ISA_MSTR_IO_LOCAL + 0x0841)#define z85230_PORTA_CTRL	(ISA_MSTR_IO_LOCAL + 0x0842)	/* serial 3 */#define z85230_PORTA_DATA	(ISA_MSTR_IO_LOCAL + 0x0843)/* z8536 aux timer and I/O chip */#define z8536_PORTC_DATA	(ISA_MSTR_IO_LOCAL + 0x0844)#define z8536_PORTB_DATA	(ISA_MSTR_IO_LOCAL + 0x0845)#define z8536_PORTA_DATA	(ISA_MSTR_IO_LOCAL + 0x0846)#define z8536_PORT_CTRL 	(ISA_MSTR_IO_LOCAL + 0x0847)#define ZCIO_CNTRL_ADRS 	(UINT8 *)(ISA_MSTR_IO_LOCAL + 0x847)#define ZCIO_IACK_ADRS		(UINT8 *)(ISA_MSTR_IO_LOCAL + 0x84F)#define ZCIO_DD_PORT_A          ((UINT8) 0x07)#define ZCIO_DD_PORT_B          ((UINT8) 0xC7)#define ZCIO_DD_PORT_C          ((UINT8) 0x00)/* m48TXX non volatile ram, RTC and watchdog timer */#define m48TXX_LSB_REG		(ISA_MSTR_IO_LOCAL + 0x0074)#define m48TXX_MSB_REG		(ISA_MSTR_IO_LOCAL + 0x0075)#define m48TXX_DAT_REG		(ISA_MSTR_IO_LOCAL + 0x0077)#ifdef	INCLUDE_I2C/* I2C registers */#define I2C_CTRL_REG		(ISA_MSTR_IO_LOCAL + 0x0981)#define I2C_CMD_STAT		(ISA_MSTR_IO_LOCAL + 0x0980)#endif /* INCLUDE_I2C */#ifdef INCLUDE_VPD/* Vital Product Data Support */#define VPD_BRD_EEPROM_ADRS 0xa0    /* i2c address of board's SROM */#define VPD_TM_EEPROM_ADRS  0xa4    /* i2c address of transition modules SROM */#define VPD_BRD_OFFSET      0   /* offset into board's eeprom for vpd data */#define VPD_TM_OFFSET       0   /* offset into tm's eeprom for vpd data */#define VPD_PKT_LIMIT       25  /* Max number of packets expected */#endif /* INCLUDE_VPD *//* CPU type */#define CPU_TYPE		((vxPvrGet() >> 16) & 0xffff)#define CPU_TYPE_601		0x01	/* PPC 601 CPU */#define CPU_TYPE_602		0x02	/* PPC 602 CPU */#define CPU_TYPE_603		0x03	/* PPC 603 CPU */#define CPU_TYPE_603E		0x06	/* PPC 603e CPU */#define CPU_TYPE_603P		0x07	/* PPC 603p CPU */#define CPU_TYPE_750		0x08	/* PPC 750 CPU */#define CPU_TYPE_604		0x04	/* PPC 604 CPU */#define CPU_TYPE_604E		0x09	/* PPC 604e CPU */#define CPU_TYPE_604R		0x0A	/* PPC 604r CPU *//* L2CR register (MPC750 - Arthur) */#define MPC750_L2CR_E		0x80000000#define MPC750_L2CR_256K	0x10000000#define MPC750_L2CR_512K	0x20000000#define MPC750_L2CR_1024K	0x30000000#define MPC750_L2CR_I		0x00200000#define MPC750_L2CR_SL		0x00008000#define MPC750_L2CR_IP		0x00000001/* System Configuration register */#define SYS_REG_GCR		((unsigned int *)(FALCON_BASE_ADRS + 0x08))#define SYS_REG_GCR_MSK 	0x0000011e#define SYS_REG_GCR_FREF	0x00000008#define SYS_REG_GCR_DRAM_70ns	0x00000000#define SYS_REG_GCR_DRAM_60ns	0x00000002#define SYS_REG_GCR_DRAM_50ns	0x00000006#ifdef CONFIG1_SYS_REG_CCR#   define SYS_REG_CCR_ 	(FALCON_BASE_ADRS + 0x400)#   define SYS_REG_CCR		((unsigned int *)(FALCON_BASE_ADRS + 0x400))#   define SYS_REG_CCR_ID_MSK		0xff000000	/* System ID mask */#   define SYS_REG_CCR_MCP750		0xfc000000	/* MCP750 board type */#   define SYS_REG_CCR_MCPN750		0xf9000000	/* MCPN750 board type */#   define SYS_REG_CCR_CLK_MSK		0x00f00000	/* Bus clock Mask */#   define SYS_REG_CCR_CPU_CLK_66	0x00f00000 /* cpu ext Bus clk 66 Mhz */#   define SYS_REG_CCR_CPU_CLK_60	0x00e00000 /* cpu ext Bus clk 60 Mhz */#   define SYS_REG_CCR_CPU_CLK_50	0x00d00000 /* cpu ext Bus clk 50 Mhz */#   define SYS_REG_CCR_SYSXC_MSK	0x000f0000 /* lkaside l2 cache mask */#   define SYS_REG_CCR_SYSXC_256	0x000e0000 /* lkaside 256kb L2 cache */#   define SYS_REG_CCR_SYSXC_512	0x000d0000 /* lkaside 512kb L2 cache */#   define SYS_REG_CCR_SYSXC_1024	0x000c0000 /* lkaside 1Mb L2 cache */#   define SYS_REG_CCR_SYSXC_NC 	0x000f0000 /* lkaside no cache */#   define SYS_REG_CCR_P0STAT_MSK	0x0000f000 /* in-line l2 cache mask */#   define SYS_REG_CCR_P0STAT_256	0x00006000 /* in-line 256kb L2 cache */#   define SYS_REG_CCR_P0STAT_512	0x00005000 /* in-line 512kb L2 cache */#   define SYS_REG_CCR_P0STAT_1024	0x00004000 /* in-line 1Mb L2 cache */#   define SYS_REG_CCR_P0STAT_NC	0x00007000 /* in-line no cache */#endif /* CONFIG1_SYS_REG_CCR *//* DRAM configuration registers */#ifdef CONFIG1_SYS_REG_MCR#   define SYS_REG_MCR_ 	(FALCON_BASE_ADRS + 0x404)#   define SYS_REG_MCR		((unsigned int *)(FALCON_BASE_ADRS + 0x404))#   define SYS_REG_MCR_FREF_UNK 	0x10000000#   define SYS_REG_MCR_FREF_TRUE	0x10000000#   define SYS_REG_MCR_FREF_FALSE	0x00000000#   define SYS_REG_MCR_DRAM_MSK 	0x03000000#   define SYS_REG_MCR_DRAM_50ns	0x03000000#   define SYS_REG_MCR_DRAM_60ns	0x01000000#   define SYS_REG_MCR_DRAM_70ns	0x00000000#   define SYS_REG_MCR_ROMAB_MSK	0x00700000#   define SYS_REG_MCR_ROMAB_ITL	0x00600000#   define SYS_REG_MCR_ROMAB_UNK	0x00700000#   define SYS_REG_MCR_L2TYPE_MSK	0x0000F000#   define SYS_REG_MCR_L2TYPE_LWP	0x00000000#   define SYS_REG_MCR_L2TYPE_BP	0x00001000#   define SYS_REG_MCR_L2TYPE_LWNP	0x00002000#   define SYS_REG_MCR_L2TYPE_BNP	0x00003000#   define SYS_REG_MCR_L2PLL_MSK	0x00000F00#   define SYS_REG_MCR_L2PLL_DIS	0x00000000#   define SYS_REG_MCR_L2PLL_1_1	0x00000100#   define SYS_REG_MCR_L2PLL_3_2	0x00000200#   define SYS_REG_MCR_L2PLL_2_1	0x00000300#   define SYS_REG_MCR_L2PLL_5_2	0x00000400#   define SYS_REG_MCR_L2PLL_3_1	0x00000500#   define SYS_REG_MCR_FLASH_MSK	0x00000038#   define SYS_REG_MCR_FLASH_1M 	0x00000000#   define SYS_REG_MCR_FLASH_2M 	0x00000008#   define SYS_REG_MCR_FLASH_4M 	0x00000010#   define SYS_REG_MCR_FLASH_8M 	0x00000018#   define SYS_REG_MCR_FLASH_16M	0x00000020#   define SYS_REG_MCR_FLASH_32M	0x00000028#   define SYS_REG_MCR_FLASH_64M	0x00000030#   define SYS_REG_MCR_FLASH_NO 	0x00000038#endif /* CONFIG1_SYS_REG_MCR */#ifdef CONFIG2_SYS_REG_MCR#   define SYS_REG_MCR_ 	(FALCON_BASE_ADRS + 0x404)#   define SYS_REG_MCR		((unsigned int *)(FALCON_BASE_ADRS + 0x404))#   define SYS_REG_MCR_MSIZ_MSK 	0xC0000001#   define SYS_REG_MCR_MSIZ_16M 	0x00000000#   define SYS_REG_MCR_MSIZ_32M 	0x40000000#   define SYS_REG_MCR_MSIZ_64M 	0x80000000#   define SYS_REG_MCR_MSIZ_128M	0xC0000000#   define SYS_REG_MCR_MSIZ_256M	0x00000001#   define SYS_REG_MCR_FREF_UNK 	0x10000000#   define SYS_REG_MCR_FREF_TRUE	0x10000000#   define SYS_REG_MCR_FREF_FALSE	0x00000000#   define SYS_REG_MCR_DRAM_MSK 	0x03000000#   define SYS_REG_MCR_DRAM_50ns	0x03000000#   define SYS_REG_MCR_DRAM_60ns	0x01000000#   define SYS_REG_MCR_DRAM_70ns	0x0#   define SYS_REG_MCR_ROMAB_MSK	0x00700000#   define SYS_REG_MCR_ROMAB_ITL	0x00600000#   define SYS_REG_MCR_ROMAB_UNK	0x00700000#   define SYS_REG_MCR_L2TYPE_MSK	0x0000F000#   define SYS_REG_MCR_L2TYPE_LWP	0x00000000#   define SYS_REG_MCR_L2TYPE_BP	0x00001000#   define SYS_REG_MCR_L2TYPE_LWNP	0x00002000#   define SYS_REG_MCR_L2TYPE_BNP	0x00003000#   define SYS_REG_MCR_L2PLL_MSK	0x00000F00#   define SYS_REG_MCR_L2PLL_DIS	0x00000000#   define SYS_REG_MCR_L2PLL_1_1	0x00000100#   define SYS_REG_MCR_L2PLL_3_2	0x00000200#   define SYS_REG_MCR_L2PLL_2_1	0x00000300#   define SYS_REG_MCR_L2PLL_5_2	0x00000400#   define SYS_REG_MCR_L2PLL_3_1	0x00000500#   define SYS_REG_MCR_FLASH_MSK	0x00000038#   define SYS_REG_MCR_FLASH_1M 	0x00000000#   define SYS_REG_MCR_FLASH_2M 	0x00000008#   define SYS_REG_MCR_FLASH_4M 	0x00000010#   define SYS_REG_MCR_FLASH_8M 	0x00000018#   define SYS_REG_MCR_FLASH_16M	0x00000020#   define SYS_REG_MCR_FLASH_32M	0x00000028#   define SYS_REG_MCR_FLASH_64M	0x00000030#   define SYS_REG_MCR_FLASH_NO 	0x00000038#endif /* CONFIG2_SYS_REG_MCR */#define DRAM_REG_SIZE		(FALCON_BASE_ADRS + 0x10)#define DRAM_REG_BASE		(FALCON_BASE_ADRS + 0x18)/* Base Module Feature Register */#ifdef CONFIG1_SYS_REG_BMFR#   define SYS_REG_BMFR 	((char *)(ISA_MSTR_IO_LOCAL + 0x0802))#   define SYS_REG_BMFR_SCCP	0x40	/* z85230 sync serial Port */#   define SYS_REG_BMFR_RSV1	0x20	/* reserved */#   define SYS_REG_BMFR_PMCP	0x10	/* pmc Present */#   define SYS_REG_BMFR_RSV2	0x08	/* reserved */#   define SYS_REG_BMFR_RSV3	0x04	/* reserved */#   define SYS_REG_BMFR_LANP	0x02	/* ethernet Present */#   define SYS_REG_BMFR_RSV4	0x01	/* reserved */#endif#ifdef CONFIG2_SYS_REG_BMFR#   define SYS_REG_BMFR 	((char *)(ISA_MSTR_IO_LOCAL + 0x0802))#   define SYS_REG_BMFR_RSV1	0x40	/* z85230 sync serial Port */#   define SYS_REG_BMFR_PMC2P	0x20	/* PMC slot 2 card present */#   define SYS_REG_BMFR_PMC1P	0x10	/* PMC slot 1 card present */#   define SYS_REG_BMFR_RSV2	0x08	/* reserved */#   define SYS_REG_BMFR_RSV3	0x04	/* reserved */#   define SYS_REG_BMFR_LANP	0x02	/* ethernet Present */#   define SYS_REG_BMFR_RSV4	0x01	/* reserved */#endif#define DEVICE_PRESENT(x)	(!((*SYS_REG_BMFR) & (x)))/* Base Module Status Register */#ifdef CONFIG1_SYS_REG_BMSR#   define	SYS_REG_BMSR	((char *)(ISA_MSTR_IO_LOCAL + 0x0803))#endif#define SYS_REG_BMSR_MCP750	0xe0	/* MCP750 */#define SYS_REG_BMSR_MCPN750	0xe1	/* MCPN750 *//* Base Module Extended Features Register */#ifdef CONFIG1_SYS_REG_BMEFR#   define SYS_REG_BMEFR	((char *)(ISA_MSTR_IO_LOCAL + 0x0810))#   define SYS_REG_BMEFR_USB1_OK	0x80	/* USB 1 Voltage sending 5V */#   define SYS_REG_BMEFR_USB0_OK	0x40	/* USB 0 Voltage sending 5V */#   define SYS_REG_BMEFR_CFPR		0x08	/* Compact FLASH Present */#   define SYS_REG_BMEFR_NVRAMP 	0x04	/* NVRAM Present */#   define SYS_REG_BMEFR_ISA_REWORK	0x02	/* Lvl sens ISA int rework */#   define SYS_REG_BMEFR_PPB1P		0x01	/* PCI-PCI bridge present */#endif#ifdef CONFIG2_SYS_REG_BMEFR#   define SYS_REG_BMEFR	((char *)(ISA_MSTR_IO_LOCAL + 0x0810))#   define SYS_REG_BMEFR_USB1_OK	0x80	/* USB 1 Voltage sending 5V */#   define SYS_REG_BMEFR_USB0_OK	0x40	/* USB 0 Voltage sending 5V */#   define SYS_REG_BMEFR_TMPRSNT	0x20	/* USB 0 Voltage sending 5V */#   define SYS_REG_BMEFR_RSV1		0x08	/* reserved */#   define SYS_REG_BMEFR_NVRAMP 	0x04	/* NVRAM Present */#   define SYS_REG_BMEFR_RSV2		0x01	/* reserved */#endif#define EXTENDED_FEATURE_PRESENT(x) (!((*SYS_REG_BMEFR) & (x)))/* SYSLED Register */#ifdef CONFIG1_SYS_REG_SYSLED#   define SYS_REG_SYSLED	((char *)(ISA_MSTR_IO_LOCAL + 0x0820))#   define SYS_REG_SYSLED_SYSEN_	0x04	/* System Slot Identification */#   define SYS_REG_SYSLED_GRN_LEN	0x02	/* Green LED */#   define SYS_REG_SYSLED_YEL_LEN	0x01	/* Yellow LED */#endif/* Board Status Register */#ifdef CONFIG1_SYS_REG_BSR#   define SYS_REG_BSR		((char *)(ISA_MSTR_IO_LOCAL + 0x0824))#   define SYS_REG_BSR_LAN_OK	0x10	/* Ethernet channel ok */#   define SYS_REG_BSR_USB_OK	0x08	/* USB channels ok */#   define SYS_REG_BSR_CPCI_OK	0x04	/* CompactPCI ok */#   define SYS_REG_BSR_BOOT_OK	0x02	/* Boot ok */#   define SYS_REG_BSR_ONLINE	0x01	/* Board online */#endif/* Board Last Reset Register */#ifdef CONFIG1_SYS_REG_BLRR#   define SYS_REG_BLRR 	((char *)(ISA_MSTR_IO_LOCAL + 0x0828))#   define SYS_REG_BLRR_PBRST	0x80	/* cPCI push button reset */#   define SYS_REG_BLRR_SWSRST	0x40	/* Software Soft Reset */#   define SYS_REG_BLRR_SWHRST	0x20	/* Software Hard Reset, port 92 */#   define SYS_REG_BLRR_RSV1	0x10	/* reserved */#   define SYS_REG_BLRR_RSV2	0x08	/* reserved */#   define SYS_REG_BLRR_WDT2	0x04	/* Watchdog Timer Level 2 Reset */#   define SYS_REG_BLRR_FBTN	0x02	/* Front Panel Button Reset */#   define SYS_REG_BLRR_PWRON	0x01	/* Power-On Reset */#endif#ifdef CONFIG2_SYS_REG_BLRR#   define SYS_REG_BLRR 	((char *)(ISA_MSTR_IO_LOCAL + 0x0828))