boot device          : dc        processor number     : 0        host name            : sunray        inet on ethernet (e) : 124.170.16.109        inet on backplane (b): 124.200.200.2:ffffff00        host inet (h)        : 124.170.16.143        gateway inet (g)     : 124.170.16.233        target name (tn)     : alpha   MCPN750-2:        #define SM_OFF_BOARD TRUE        #undef  SYS_SM_SYSTEM_MEM_POLL        #undef  INCLUDE_SM_SEQ_ADDR        boot device          : sm        processor number     : 2        host name            : sunray        inet on ethernet (e) : 124.170.16.110        inet on backplane (b): 124.200.200.3        host inet (h)        : 124.170.16.143        gateway inet (g)     : 124.200.200.2        target name (tn)     : beta.CE.ne 6.IP "6)"MCPN750 master, MCPN750 anchor, sequential addressing:.CS   MCP750:        #define SM_OFF_BOARD TRUE        #undef  SYS_SM_SYSTEM_MEM_POLL        /* #undef  INCLUDE_SM_SEQ_ADDR */        boot device          : sm        processor number     : 1        host name            : sunray        inet on ethernet (e) :        inet on backplane (b):        host inet (h)        : 124.170.16.143        gateway inet (g)     :        target name (tn)     : gamma   MCPN750-1:        #define SM_OFF_BOARD FALSE        #undef  SYS_SM_SYSTEM_MEM_POLL        /* #undef  INCLUDE_SM_SEQ_ADDR */        boot device          : dc        processor number     : 0        host name            : sunray        inet on ethernet (e) : 124.170.16.109:ffffff00        inet on backplane (b): 124.200.200.1:ffffff00        host inet (h)        : 124.170.16.143        gateway inet (g)     : 124.170.16.233        target name (tn)     : alpha   MCPN750-2:        #define SM_OFF_BOARD TRUE        #undef  SYS_SM_SYSTEM_MEM_POLL        /* #undef  INCLUDE_SM_SEQ_ADDR */        boot device          : sm        processor number     : 2        host name            : sunray        inet on ethernet (e) :        inet on backplane (b):        host inet (h)        : 124.170.16.143        gateway inet (g)     :        flags (f)            : 0x0        target name (tn)     : beta.CE.SS "Unsupported Features"The following board features are not supported:.TS Eexpand;lf3 lf3lw13 lw(3.7i) ..ne 6.sp .5Feature	Description_DRAM	T{ECC protectionT}RTC	T{MK48T59/559; only NVRAM portion is usedT}Peripherals	T{PS/2 keyboard port;PS/2 mouse port;IEEE1284/printer parallel port;SROM (I2C interface)T}ISA Interface	T{ISA RTCT}PCI Interface	T{64-bit data; Prefetchable memory is not distinguished from nonprefetchable.T}.TE.SS "Feature Interactions"None known..SH "HARDWARE DETAILS"This section details device drivers and board hardware elements..SS "Devices"The device drivers and libraries included with this BSP:.nf    `i8250Sio' - Intel 8250 UART driver (serial ports 1 and 2)    `z8530Sio' - Zilog Z8530 SCC/Z85230 ESCC driver (serial ports 3 and 4)    `ppcDecTimer' - PowerPC decrementer timer driver (system clock)    `ppcZ8536Timer' - Zilog Z8536 timer driver (auxiliary and timestamp clock)    `ravenAuxClk' - Motorola Raven timer driver for auxiliary clock    `ravenMpic' - Motorola Raven MPIC interrupt controller driver    `ravenPci' - Motorola Raven PCI bus bridge chip driver    `pciAutoConfigLib' - PCI autoconfiguration library    `pciConfigLib' - PCI configuration library    `pciConfigShow' - Show routines of PCI bus library    `if_dc' - 10baseT/100baseTX DEC 21140 Ethernet driver (primary LAN)    `byteNvRam' - byte-oriented generic non-volatile RAM driver    `ns8730xSuperIo' - National Semiconductor 8730x Super IO driver    `ataDrv' - ATA/IDE (LOCAL and PCMCIA) disk device driver    `fdcDrv' - floppy disk controller (FDC) Input/Output driver    `isaDma' - DMA controller device (I8237) utilities/support driver    `ncr810Lib' - NCR 53C825 SCSI controller library.fi.SS "Memory Maps"On-board RAM for these boards always appears at address 0x0 locally.Dynamic memory sizing is supported.  By default, LOCAL_MEM_AUTOSIZE isdefined so memory is auto-sized at hardware initialization time.If auto-sizing is not selected, LOCAL_MEM_SIZE must be set to the actual sizeof DRAM memory available on the board to ensure all memory is available.The default fixed RAM size is set to 16MB (see LOCAL_MEM_SIZE in config.h)..SS "Interrupts"The system interrupt vector table has 256 entries.  Vectors for the variousdevices on the buses are assigned hierarchically as follows:.TS Ccenter;lf3 lf3l lw(2.6i) ..ne 6.sp .5Vector#	Assigned to_00 - 0f	ISA IRQ numbers 0 - 1510 - 1f	All MPIC interrupts20 - 23	Raven timers24 - 27	Raven interprocessor dispatch   28  	Raven detected internal errors29 - ff	[User defined].TEThe specific ISA vector number assignments are:.TS Ccenter;lf3 lf3l lw(2.6i) ..ne 6.sp .5Vector#	Assigned to_   02	[Cascade interrupt from PIC2]   03	COM2   04	COM1   09	Aux timers; serial ports 3 and 4.TEVector numbers not in the table are not used by this BSP.The standard ISA Intel 8259 Programmable Interrupt Controllers (PICs) asserttheir interrupts through the Raven MPIC as an external interrupt.  The externalinterrupt vector numbers are:.TS Ccenter;lf3 lf3l lw(2.6i) ..ne 6.sp .5Vector#	Assigned to_   10	PBC (8259)   11	Falcon-ECC error   12	PCI Ethernet   13	PMC INT (OR of INTA# - INTD#)   14	Watchdog Timer Level 1   15	CompactPCI PRST# signal   16	CompactPCI FAL# signal   17	CompactPCI DEG# signal   18	CompactPCI Bus1 INTA#   19	CompactPCI Bus1 INTB#   1a	CompactPCI Bus1 INTC#   1b	CompactPCI Bus1 INTD#   1c	CompactPCI Bus2 INTA#   1d	CompactPCI Bus3 INTB#   1e	CompactPCI Bus4 INTC#   1f	CompactPCI Bus5 INTD#.TEVector numbers not in the table are not used by this BSP.The Raven Multi-Processor Interrupt Controller (MPIC) sets system interruptpriorities and serves as controller of all external interrupts.  Eachof its 16 interrupt control registers, designated IRQ0 through IRQ15, can beprogrammed with a relative priority from 15, the highest, to 0, the lowest.  Apriority of zero effectively disables the interrupt.  All but one of the 16control registers has been hardwired to a particular interrupt source.  The IRQnumber and priority assignments are as follows:.TS Eexpand;lf3 lf3 lf3l l lw(2.6i) ..ne 6.sp .5Raven MPIC IRQ	Priority	IRQ Source_IRQ0	8	PBC (8259)IRQ1	0	Falcon ECC ErrorIRQ2	14	EthernetIRQ3	3	PMC INTIRQ4	0	Watchdog Timer Level 1IRQ5	10	CompactPCI PRST# signalIRQ6	0	CompactPCI FAL# signalIRQ7	0	CompactPCI DEG# signalIRQ8	0	CompactPCI Bus 1 INTA#IRQ9	7	CompactPCI Bus 1 INTB#IRQ10	6 	CompactPCI Bus 1 INTC#IRQ11	5	CompactPCI Bus 1 INTD#IRQ12	4	CompactPCI Bus 2 INTA#IRQ13	0	CompactPCI Bus 2 INTB#IRQ14	15	CompactPCI Bus 2 INTC#IRQ15	0	CompactPCI Bus 2 INTD#.TEFor further details, refer to the appropriate board's reference guide.There are only four PCI bus interrupts: A, B, C, and D.  They are shared amongall PCI bus devices and do not have levels.  PCI bus interrupts are wireddirectly to the MPIC and, therefore, have pre-assigned system vector numbersand interrupt levels.  The user enables one or more PCI interrupts and connectsvectored ISRs to the system by following these steps:.IP "1)"Identify the PCI interrupt letter(s) as required bythe application. Based on this, identify theassociated system interrupt level from the followingtables:            Primary PCI Bus            ----------------            A = PMC_INT_LVL1            B = PMC_INT_LVL2            C = PMC_INT_LVL3            D = PMC_INT_LVL4            Secondary PCI Bus            -----------------            A = PMC_INT_LVL4            B = PMC_INT_LVL3            C = PMC_INT_LVL2            D = PMC_INT_LVL1.IP "2)"Define the vector for each PCI interrupt as follows:INT_VEC_IRQ0 + PMC_INT_LVLx where x is 1, 2, 3, or 4,as determined above..IP "3)"In the application code, perform intConnect() foreach vector and its associated ISR..IP "4)"Perform IntEnable() for each identified system interrupt level..IP "5)"When the application has finished, performIntDisable() for each identified level..SS "Address Translation"To assist with address translation, two translation routines areprovided by this BSP:.TS Ccenter;rw20 lw(3.2i) .sysLocalToBusAdrs()	T{Translates a local CPU address to an equivalent cPCI or local PCI memory orI/O address.T}sysBusToLocalAdrs()	T{Translates a cPCI or local PCI memory or I/O space address to a local CPUequivalent address.T}.TEThese routines accept the address space designators defined in "pci.h".Since access to the Compact PCI bus is through a transparent PCI-to-PCI bridge,the local PCI and Compact PCI busses share a common address space.As a result, the local and backpanel address designators in "pci.h" map tothe same address spaces and the translation for both ranges is identical. Forexample, PCI_LOCAL_IO_SPACE and PCI_BACKPANEL_IO_SPACE would both referencethe same address space.Note that although there are two PCI memory spaces (normal PCIMemory space and PCI Memory I/O space), they share a single addressspace. In other words, PCI memory address 0x1000 cannot exist as normalPCI Memory and PCI Memory I/O simultaneously. The translation routinestherefore treat both PCI Memory and PCI Memory I/O as a single addressspace..SS "Serial Configuration"The MCP750 has four serial ports.  All are ISA bus devices.Two, serial port 1 (COM1 or console) and serial port 2 (COM2),originate from the PC87308 Super I/O (SIO) chip.  The SIO serial ports arefunctional equivalents to those in an Intel 8250 UART.