/* config.h - Motorola PowerPlus board configuration header *//* Copyright 1984-2002 Wind River Systems, Inc. *//* Copyright 1996,1997,1998,1999 Motorola, Inc., All Rights Reserved *//*modification history--------------------02z,17jun02,mil Updated shared memory macros for Tornado 2.2.02y,23may02,mil Updated INCLUDE_AUXCLK to INCLUDE_AUX_CLK.02x,10apr02,mil Updated shared memory macros for Tornado 2.2.02w,07dec01,wef add USB macros02v,26nov01,mil Updated BSP revision for Tornado 2.2.02u,15dec99,rhv Added support for non-MCPN750 cPCI boards.02t,10nov99,tm  Defined cPCI bus 2 MPIC priorities for mcp750 (SPR 29402)02s,10jun99,tm  Added PCI_CFG_TYPE = PCI_CFG_AUTO in config.h02r,01jun99,srr Replaced SM_INT_ARG2 calculation with a function call.                Modify drawbridge translation window to match with new                address used for dynamic pci allocation.02q,20may99,tm  Added INCLUDE_BSD so attach is called for netif (only) sm driver02p,17may99,tm  Added Tornado 2.0 support: BSP_VER_1_2, project build02o,29apr99,scb Change anchor back to 0x4100, move SM_MEM_ADRS to unused place.02n,30apr99,srr Enable roll call by default.02m,09apr99,srr Code Review changes: Changed RAM_HIGH_ADRS to 8 MB,                Changed BSP revisions.                Changed to WRS address space naming convention.                Removed NETIF driver references.                Removed MOTOROLA_21143_SROM_FIX.                Remove non-standard CompactPCI interrupt support.                Remove non-standard CompactPCI interrupt support.                Remove INCLUDE_DC references and support.02l,23mar99,scb Made SM_INT_ARG2 for mailbox ints byte-long, not word-long.02k,26feb99,scb Introduced PCI_SYSTEM_DRAM_ADRS for shared memory workings with                  a CPV5000.02j,22feb99,scb Moved PCI2DRAM_BASE_ADRS definition into "config.h".02i,29jan99,srr changed MCPN750 revision to 0.3 for MCG factory release.02h,27jan99,scb Code cleanup involving INCLUDE_SCSI.02g,22jan99,scb Removed ROM_BASED & added PCI_AUTOCONFIG_DONE macro.02f,18jan99,scb Added mod to control DEC21143 SROM formatting problem.02e,08dec98,scb Fixed bugs in ROM_BASED macro.02d,01dec98,scb Moved SM_ANCHOR_OFFSET to 0x4500, SM_MEM_ADRS = SM_ANCHOR_OFFSET02c,18nov98,scb Added global flag setting to indicate non ROM based.02b,13nov98,scb INCLUDE_AUXCLK for mpcn750, SM_MEM_ADRS in safe place.02a,09nov98,srr changed MCPN750 revision to 0.2 for MCG factory release.01z,05nov98,scb Add shared memory support for nonhost node zero.01y,28oct98,rhv Changed SM_TAS_TYPE to SM_TAS_HARD to use a modified software                TAS algorithm. Set all cPCI interrupt levels equal.01x,02sep98,scb Modified presentation of "roll call" support.01w,21sep98,rhv Added Vital Product Data support (VPD).01v,08sep98,rhv Added CPCI_FLUSH_ADDR for cPCI Bus Probe support.01u,04sep98,scb Added shared memory support (MCP750 master and mem repository)01t,28aug98,rhv Adding processor data bus parity control defines.01s,05aug98,rhv Removing commented PCI_BAR_MEM_PREFETCH from Dec2155x memory                type definitions and adding comment with instructions on how                to make memory windows pre-fetchable instead.01r,04aug98,rhv Changed priority level of Dec2155x interrupt.01q,03aug98,srr chaged revision to 2.1 for MCG MPCN750 Pre-Release.01p,31jul98,scb Modified MPIC level sensitive comment.01o,30jul98,rhv Dec2155x window parameter cleanup.01n,30jul98,scb Added PCI_MEM_SPACE use.01m,29jul98,rhv Add Dec2155x support.01l,29jul98,scb Name change from "mv2600.h" to "mcpx750.h"01k,21jul98,scb Include only MCP750 and MCPN750 support.01j,07jul98,scb Initial support for MCPN750.01i,26jun98,srr disable ATA_DEV1_STATE.01h,09jun98,mas rev 1 -> 2 for mcp750 release.01g,02jun98,tm  revert to Mot autoconfig code and MCP750 dependencies01f,14may98,tm  added INCLUDE_PCI_AUTOCONF and INCLUDE_ECC01e,16apr98,db  added floppy disk support01d,13apr98,db  merge from Motorola bsp(macro INCLUDE_PCI added).01c,15jan98,srr changed auxiliary clock for MCP750 to use Raven timer.01b,13jan98,srr changed revision to 0.2 for MCG factory release.01a,09jan98,rhk created (from ver 02d, mv2600/config.h)*//* * This file contains the configuration parameters for the * Motorola PowerPlus architecture */#ifndef	INCconfigh#define	INCconfigh#ifdef __cplusplusextern "C" {#endif/* The following defines must precede configAll.h *//* BSP version/revision identification */#define BSP_VER_1_1     1#define BSP_VER_1_2     1#define BSP_VERSION     "1.2"#define BSP_REV         "/5"		/* 0 for first revision *//* PRIMARY INCLUDES */#include "configAll.h"#include "sysMotCpci.h"/* defines */#define DEFAULT_BOOT_LINE \	"dc(0,0)host:/tornado/mcp750/vxWorks h=90.0.0.1 e=90.0.0.2 u=vxworks"#define WRONG_CPU_MSG "An MPC750 VxWorks image cannot run on a PPC603!\n";/* * The following cPCI address accesses the beginning of system * (cPCI master) DRAM.  This should be set to: *     0x80000000 if the cPCI master is a MCP750; *     0x00000000 if the cPCI master is a CPV5000. */#define CPCI_MSTR_MEM_BUS	0x80000000/* * Default board configurations * * If a supported feature is desired, *         change to: #define * If a feature is not desired or not supported *         change to: #undef * * NOTE: Not all functionality is supported on all boards */#ifdef MCP750#   define	INCLUDE_ECC		/* ECC Memory Support */#   define	INCLUDE_CACHE_L2	/* L2 cache support */#   define	INCLUDE_I8250_SIO       /* COM1 and COM2 via i8250 */#   define	INCLUDE_Z85230_SIO      /* serial ports 3 & 4 via Z85230 */#   define	INCLUDE_AUX_CLK		/* Raven aux clock */#   define	INCLUDE_PCI		/* include the PCI library support */#   undef	INCLUDE_ATA		/* ATA-2 portion of EIDE support */#   undef	INCLUDE_SCSI		/* PMC module SCSI (user supplied) */#   undef 	INCLUDE_FD		/* [OPTIONAL] Floppy Disk  */#   undef       INCLUDE_DPE	        /* Processor data bus parity enable */#   undef       INCLUDE_VPD             /* Vital Product Data unsupported */#   define	SM_INT_TYPE  SM_INT_BUS /* cPCI bus interrupt */#   define	SM_INT_ARG3  0          /* Not used with SM_INT_BUS */#   define	SM_OFF_BOARD FALSE	/* Memory pool is on-board */    /*      * Change PCI_MSTR_MEMIO_SIZE to reflect the size of the PCI memory space     * that is mapped in the sysPhysMemDesc[] array (in sysLib.c) for PCI     * autoconfiguration.     *     * Be aware that all of the space starting with PCI_MSTR_MEMIO_LOCAL     * (0xc0000000) and continuing for PCI_MSTR_MEMIO_SIZE bytes will be     * mapped with MMU tables.  For each 128K of memory in this region,     * a 1K piece of RAM will be used for MMU tables.  If the region is very     * large, modifications to sysLib.c can be made to use BAT (Block Address     * Translation) registers instead of MMU page tables to map the memory.     * Note that the window defined by altering PCI_MSTR_MEMIO_SIZE must be     * large enough to accomodate all of the PCI memory space found during     * PCI autoconfiguration.  If it is not, some devices will not be     * autoconfigured.     */ #   define PCI_MSTR_MEMIO_SIZE	0x02000000	/* 32 MB */#   define PCI_MSTR_MEM_SIZE	0x00800000	/* 8 MB */#endif  /* MCP750 */#ifdef MCPN750#   define	INCLUDE_ECC		/* DRAM ECC support */#   define	INCLUDE_CACHE_L2	/* L2 cache support */#   define	INCLUDE_I8250_SIO       /* COM1 thru COM4 are 16550 UARTS */#   define	INCLUDE_AUX_CLK		/* Raven aux clock */#   define	INCLUDE_PCI             /* PCI configuration library */#   define	INCLUDE_DEC2155X	/* Compact PCI bridge support */#   undef	INCLUDE_ATA		/* ATA-2 portion of EIDE support */#   undef	INCLUDE_SCSI		/* PMC module SCSI (user supplied) */#   define      INCLUDE_DPE	        /* Processor data bus parity enable */#   define      INCLUDE_VPD             /* Vital Product Data support */#   define      SM_INT_TYPE  SM_INT_MAILBOX_1  /* "doorbell" register int. */#   define      SM_INT_ARG3  (1 << (DEC2155X_SM_DOORBELL_BIT % 8))#   define      SM_OFF_BOARD TRUE       /* Memory pool is off-board */    /*      * Change PCI_MSTR_MEMIO_SIZE to reflect the size of the PCI memory space     * that is mapped in the sysPhysMemDesc[] array (in sysLib.c) for PCI     * autoconfiguration.     *     * Be aware that all of the space starting with PCI_MSTR_MEMIO_LOCAL     * (0xc0000000) and continuing for PCI_MSTR_MEMIO_SIZE bytes will be     * mapped with MMU tables.  For each 128K of memory in this region,     * a 1K piece of RAM will be used for MMU tables.  If the region is very     * large, modifications to sysLib.c can be made to use BAT (Block Address     * Translation) registers instead of MMU page tables to map the memory.     * Note that the window defined by altering PCI_MSTR_MEMIO_SIZE must be     * large enough to accomodate all of the PCI memory space found during     * PCI autoconfiguration.  If it is not, some devices will not be     * autoconfigured.     */ #   define PCI_MSTR_MEMIO_SIZE	0x04000000	/* 64 MB */#   define PCI_MSTR_MEM_SIZE	0x00800000	/* 8 MB */#endif  /* MCPN750 *//* MMU and Cache options */#define	INCLUDE_MMU_BASIC       /* bundled mmu support */#undef	USER_D_CACHE_MODE#define	USER_D_CACHE_MODE       (CACHE_COPYBACK | CACHE_SNOOP_ENABLE)#ifdef  INCLUDE_CACHE_L2#   define	USER_L2_CACHE_ENABLE			/* enable L2 cache */#   define	L2_CACHE_MODE	CACHE_WRITETHROUGH	/* Only 1 supported */#endif  /* INCLUDE_CACHE_L2 *//* PCI Configuration type */#define PCI_CFG_TYPE PCI_CFG_AUTO/* timestamp option not included by default;  #define to include it */#undef  INCLUDE_TIMESTAMP/* select advanced network driver support */#define	INCLUDE_END/* Primary SCSI support */#ifdef  INCLUDE_SCSI#   define	INCLUDE_SCSI2		/* Use SCSI2 library, not SCSI1 */#   define	INCLUDE_SCSI_BOOT	/* include ability to boot from SCSI */#   define	INCLUDE_DOSFS		/* file system to be used */#   undef	SCSI_AUTO_CONFIG	/* scan bus for devices on startup */#   undef	SCSI_WIDE_ENABLE	/* enable wide SCSI, 16-bit data xfrs */#   define	SYS_SCSI_CONFIG		/* call sysScsiConfig in sysScsi.c */#endif  /* INCLUDE_SCSI *//* ATA-2 portion of EIDE support */#ifdef	INCLUDE_ATA#   ifndef	INCLUDE_DOSFS#       define	INCLUDE_DOSFS		/* file system to be used */#   endif	/* INCLUDE_DOSFS */    /*     *	The ATA_DEVx_STATE determines whether the ATA driver should probe     *	for a device.  DEV_PRESENT = probe; DEV_NOT_PRESENT = don't probe.     *     *	To probe for all devices connect to both buses,     *	change all ATA_DEVx_STATE values to DEV_PRESENT.     *     *	ATA_DEV0_STATE = cntlr 0 / device 0     *	ATA_DEV1_STATE = cntlr 0 / device 1     *	ATA_DEV2_STATE = cntlr 1 / device 0     *	ATA_DEV3_STATE = cntlr 1 / device 1     */#   define	DEV_PRESENT	1#   define	DEV_NOT_PRESENT	0#   define	ATA_DEV0_STATE	DEV_PRESENT#   define	ATA_DEV1_STATE	DEV_NOT_PRESENT /* Do not alter for MCP750 */#   define	ATA_DEV2_STATE	DEV_NOT_PRESENT /* Unavailable on MCPN750 */#   define	ATA_DEV3_STATE	DEV_NOT_PRESENT /* Unavailable on MCPN750 */#endif	/* INCLUDE_ATA */#ifdef INCLUDE_DEC2155X    /* Dec2155x (Drawbridge) configuration parameters */#   define DEC2155X_SUB_VNDR_ID_VAL     MOT_SUB_VNDR_ID_VAL#   define DEC2155X_SUB_SYS_ID_VAL      MCPN750_SUB_SYS_ID_VAL#   define DEC2155X_PCI_DEV_NUMBER 0x14#   define DEC2155X_PCI_BUS_NUMBER 0x00    /*     * a PCI read from the following cPCI memory address is used to flush the     * Dec2155x write post buffer. It must be a valid location and free of     * side effects. The default value targets location 0x00000000 in host DRAM.     */#   define CPCI_FLUSH_ADDR CPCI_MSTR_MEM_BUS    /*     * NOTE: Window sizes must be an integral power of 2 and translation     * values must be an even multiple of the window size. To enable     * prefetch on a memory window "or" in PCI_BAR_MEM_PREFETCH.     */    /* Downstream windows (for access from Compact PCI backpanel) */    /*     * note that downstream translation values are relative to the local PCI     * memory map not the local processor address map. PCI_SLV_MEM_BUS is     * the base of the local DRAM as seen from the local PCI bus (secondary     * side of the 2155x).  Raven will translate this into a local DRAM address.     */    /*     * 4MB window into local DRAM (first 4KB accesses 2155x CSR register set).     */#   define DEC2155X_CSR_AND_DS_MEM0_SIZE 0x00400000#   define DEC2155X_CSR_AND_DS_MEM0_TYPE (PCI_BAR_SPACE_MEM | \                                          PCI_BAR_MEM_ADDR32)#   define DEC2155X_CSR_AND_DS_MEM0_TRANS PCI_SLV_MEM_BUS    /* Downstream windows 1, 2 and 3 not used (disabled) */#   define DEC2155X_DS_IO_OR_MEM1_SIZE   0x00000000#   define DEC2155X_DS_IO_OR_MEM1_TYPE   (PCI_BAR_SPACE_MEM | \                                          PCI_BAR_MEM_ADDR32)#   define DEC2155X_DS_IO_OR_MEM1_TRANS   0x00000000#   define DEC2155X_DS_MEM2_SIZE         0x00000000#   define DEC2155X_DS_MEM2_TYPE         (PCI_BAR_SPACE_MEM| \                                          PCI_BAR_MEM_ADDR32 )#   define DEC2155X_DS_MEM2_TRANS        0x00000000#   define DEC2155X_DS_MEM3_SIZE         0x00000000#   define DEC2155X_DS_MEM3_TYPE         (PCI_BAR_SPACE_MEM| \                                          PCI_BAR_MEM_ADDR32 )#   define DEC2155X_DS_MEM3_TRANS        0x00000000    /* Upstream windows (for access to Compact PCI backpanel) */    /*     * note that upstream translation values are relative to the Compact PCI     * memory map not the local processor address map. 0x00000000 is the     * base of PCI memory space as seen from the Compact PCI bus (primary     * side of the 2155x).     */    /* 4MB window into host (system slot) DRAM. */#    define DEC2155X_US_IO_OR_MEM0_SIZE 0x00400000#    define DEC2155X_US_IO_OR_MEM0_TYPE (PCI_BAR_SPACE_MEM | \                                         PCI_BAR_MEM_ADDR32)#   define DEC2155X_US_IO_OR_MEM0_TRANS CPCI_MSTR_MEM_BUS /* map to DRAM */    /*     * 32MB window into Compact PCI memory space to access non-system boards     * NOTE: this window must be large enough to cover the pci memory area     * configured in the host for dynamic pci device allocation. the     * translation value for this window should equal the pci memory base     * address for this area.     */#   define DEC2155X_US_MEM1_SIZE 0x02000000#   define DEC2155X_US_MEM1_TYPE (PCI_BAR_SPACE_MEM | \                                  PCI_BAR_MEM_ADDR32)#   define DEC2155X_US_MEM1_TRANS 0x00000000 /* 0xc0000000 from pci bus */#   define DEC2155X_US_MEM2_PG_SZ 0x00000000 /* close window */#endif /* INCLUDE_DEC2155X *//* serial parameters */#undef	NUM_TTY#define	NUM_TTY			N_SIO_CHANNELS/* * Auxiliary Clock support is an optional feature that is not supported * by all BSPs. */#ifdef  INCLUDE_AUX_CLK#    define INCLUDE_RAVEN_AUXCLK                /* specify aux clock device */#endif /* INCLUDE_AUX_CLK *//* * Local Memory definitions * * By default, the available DRAM memory is sized at bootup (LOCAL_MEM_AUTOSIZE * is defined).  If auto-sizing is not selected, make certain that * LOCAL_MEM_SIZE is set to the actual amount of memory on the board. * By default, it is set to the minimum memory configuration: 16 MB. * Failure to do so can cause unpredictable system behavior! */#define	LOCAL_MEM_AUTOSIZE			/* undef for fixed size */#define LOCAL_MEM_LOCAL_ADRS	0x00000000	/* fixed at zero */#define LOCAL_MEM_SIZE		0x01000000	/* Default: Min memory: 16MB */