#define RAM_HIGH_ADRS		0x00800000  	/* RAM address for ROM boot */#define RAM_LOW_ADRS		0x00100000	/* RAM address for kernel *//* user reserved memory, see sysMemTop() */#define USER_RESERVED_MEM	(0)	/* number of reserved bytes *//* * The constants ROM_TEXT_ADRS, ROM_SIZE, RAM_LOW_ADRS and RAM_HIGH_ADRS  * are defined in config.h, Makefile. * All definitions for these constants must be identical. */#undef INCLUDE_MOT_BUG_ROM			/* define this to use */#ifdef INCLUDE_MOT_BUG_ROM#   define	ROM_BASE_ADRS	(LOCAL_MEM_SIZE)#   define	ROM_TEXT_ADRS	ROM_BASE_ADRS#else#   define	ROM_BASE_ADRS	0xfff00000	/* base address of ROM */#   define	ROM_TEXT_ADRS	(ROM_BASE_ADRS + 0x100)#endif /* INCLUDE_MOT_BUG_ROM */#define	ROM_SIZE		0x00100000	/* 1MB ROM space *//* Shared-memory Backplane Network parameters *//* * INCLUDE_SM_NET and INCLUDE_SM_SEQ_ADDR are the shared memory backplane * driver and the auto address setup.  Use #define or #undef to define or * undefine them respectively. *//* #define INCLUDE_SM_NET *//* #define INCLUDE_SM_SEQ_ADDR */#ifdef INCLUDE_SM_NET#   define INCLUDE_SM_COMMON#   define INCLUDE_BSD#endif  /* INCLUDE_SM_NET */#if defined(INCLUDE_SM_COMMON) && defined(MCP750)    /*     * MAX_SM_DEVICE_COUNT must be >= actual count of shared memory     * devices present      */#   define MAX_SM_DEVICE_COUNT  7#   define DEC2155X_SYSTEM_SUPPORT#endif  /* defined(INCLUDE_SM_COMMON) && defined(MCP750) *//* * If the anchor is offboard (SM_OFF_BOARD == TRUE) then place the * anchor SM_ANCHOR_OFFSET at 0x4100 if the actual anchor is on an * MCP750 or MCPN750, or place it at 0x1100 if the actual anchor is * on a CPV5000. */#if (SM_OFF_BOARD == TRUE)#   undef  SM_ANCHOR_ADRS#   define SM_ANCHOR_ADRS   (sysSmAnchorAdrs())#   define SM_MEM_ADRS      (SM_ANCHOR_ADRS + (0x4d00 - SM_ANCHOR_OFFSET))#else#   undef  SM_ANCHOR_ADRS#   define SM_ANCHOR_ADRS   ((char *)(LOCAL_MEM_LOCAL_ADRS + SM_ANCHOR_OFFSET))#   define SM_MEM_ADRS      0x00004d00#endif  /* SM_OFF_BOARD == TRUE *//* * The following defines are only used by the master. * The slave only uses the "Anchor" address. */#ifdef INCLUDE_SM_NET#   define SM_MEM_SIZE		0x00010000#else#   define SM_MEM_SIZE		0#endif  /* INCLUDE_SM_NET */#ifdef INCLUDE_SM_OBJ#   define SM_OBJ_MEM_ADRS	(SM_MEM_ADRS+SM_MEM_SIZE) /* SM Objects pool */#   define SM_OBJ_MEM_SIZE	0x00010000#else#   define SM_OBJ_MEM_SIZE	0#endif  /* INCLUDE_SM_OBJ *//* * Finding the shared memory anchor: * * There are three ways to communicate the location of the anchor to the * initialization code: *  * 1) If "sm=xxxxxxxx" is specified as a boot parameter, then "xxxxxxxx" *    is used as the local address of the anchor. *  * 2) If case (1) above is not satisified, then if SM_OFF_BOARD is FALSE, *    the address LOCAL_MEM_LOCAL_ADRS + SM_ANCHOR_OFFSET is used as the *    local address of the anchor. *  * 3) If neither (1) or (2) above is satisified (that is "sm=xxxxxxxx" is *    NOT specified AND SM_OFF_BOARD is defined as TRUE) then the shared *    memory anchor is found via a polling algorithm as described below: * *    Devices on the compactPCI bus (defined by SYS_SM_CPCI_BUS_NUMBER) *    are queried through the first memory BAR.  Memory at offset *    SM_ANCHOR_OFFSET is examined to determine if the anchor is there.   * *    If SYS_SM_ANCHOR_POLL_LIST is defined then only those *    devices whose device/vendorID and subsystem device/vendorID *    are defined in this list are queried.  If SYS_SM_ANCHOR_POLL_LIST *    is NOT defined then ALL devices found on SYS_SM_CPCI_BUS_NUMBER *    are queried. * *    In addition if SYS_SM_SYSTEM_MEM_POLL is defined, the *    system memory (at compact PCI address CPCI_MSTR_MEM_BUS +  *    SM_ANCHOR_OFFSET) is also queried for a possible location for  *    the anchor.  If SYS_SM_SYSTEM_MEM_POLL is not defined, then  *    system memory is not polled.  This option would typically be  *    used if the anchor resided on an MCP750 and the initialization  *    code was running on an MCPN750. */#if (SM_OFF_BOARD == TRUE)#   define SYS_SM_ANCHOR_POLL_LIST SYS_MOT_SM_ANCHOR_POLL_LIST#endif#define SYS_SM_CPCI_BUS_NUMBER    1 #define SYS_SM_SYSTEM_MEM_POLL/* * SM_INT_ARG1 is calculated in sysSmParamsCompute(), "sysLib.c" * SM_INT_ARG2 is dynamically calculated in sysSmArg2Compute(), "sysLib.c" */ #ifndef _ASMLANGUAGEIMPORT  char * sysSmAnchorAdrs();IMPORT	int    smIntArg1;int	sysSmArg2Compute (void);#endif#define SM_INT_ARG1 (smIntArg1)#define SM_INT_ARG2 (sysSmArg2Compute())/* * The array fragment below lists Dec2155x-based cPCI boards which participate * in shared memory backplane networking. The boards are listed by subsystem * vendor ID and subsystem ID. To add new boards, simply add them to the list. * NOTE: This list only applies to Dec2155x-based boards. There is currently no * equivalent mechanism for other boards since this BSP only contains interrupt * drivers for the Dec2155x. */#ifdef DEC2155X_SYSTEM_SUPPORT#   define SYS_SM_DEVICE_LIST	SYS_MOT_SM_DEVICE_LIST#endif  /* DEC2155X_SYSTEM_SUPPORT *//* * Note: MCP750/MCPN750 requires a modified software Test and Set algorithm. * SM_TAS_TYPE is set to SM_TAS_HARD despite the lack of a hardware TAS * mechanism to force the use of a BSP-specific software TAS algorithm. The * modified algorithm is required to work around a problem encountered with * PCI-to-PCI bridges. */#undef SM_TAS_TYPE#define SM_TAS_TYPE 	SM_TAS_HARD/* * The following must be a value between 0 and 15.  It represents the  * bit number of the primary doorbell register used to interrupt the  * MCP750 for shared memory * bus interrupts.  */#define DEC2155X_SM_DOORBELL_BIT 0/* * These defines are used to initialize the External Source * Vector/Priority registers in the MPIC.  The following can * be defined: interrupt sensitivity, polarity and interrupt priority. * * Note: by default a 1 into the sense bit(22) will set up for active * low (interrupt sources 1 thru 15).  A 1 into the polarity bit * affects only interrupt source zero and sets it up for high level * sensitive interrupts. * * At initialization all external interrupt sources are disabled * except for the 8259 input, which is enabled in the MPIC driver. * * All currently unused interrupt sources are set to a priority of * 0, which will not allow them to be enabled.  If any one of these * levels is to be used, the priority value must be changed here. */ #ifdef MCP750#   define INIT_EXT_SRC0	( INT_MASK_BIT | HIGH_POLARITY | LEVEL_SENSE |\				  PRIORITY_LVL8 )   /* PIB (8259) */ #   define INIT_EXT_SRC1	( INT_MASK_BIT | PRIORITY_LVL0 ) /* Falcon ECC*/ #   define INIT_EXT_SRC2	( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL14 )  /* primary ethernet */ #   define INIT_EXT_SRC3	( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL3 )   /* PCI Mezzanine card  */#   define INIT_EXT_SRC4	( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL0 )   /* Watchdog Timer Level 1 */#   define INIT_EXT_SRC5	( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL0 )  /* cPCI PRST# */ #   define INIT_EXT_SRC6	( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL0 )   /* cPCI FAL# */#   define INIT_EXT_SRC7	( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL0 )   /* cPCI DEG# */ #   define INIT_EXT_SRC8	( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL8 )   /* cPCI bus 1 INTA */#   define INIT_EXT_SRC9	( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL8 )   /* cPCI bus 1 INTB */				 #   define INIT_EXT_SRC10	( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL8 )   /* cPCI bus 1 INTC */ #   define INIT_EXT_SRC11	( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL8 )   /* cPCI bus 1 INTD */#   define INIT_EXT_SRC12	( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL8 )   /* cPCI bus 2 INTA */#   define INIT_EXT_SRC13	( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL8 )   /* cPCI bus 2 INTB */ #   define INIT_EXT_SRC14	( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL8 )   /* cPCI bus 2 INTC */ #   define INIT_EXT_SRC15	( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL8 )   /* cPCI bus 2 INTD */#endif /* MCP750 */#ifdef MCPN750#   define INIT_EXT_SRC0	( INT_MASK_BIT | HIGH_POLARITY | LEVEL_SENSE |\				  PRIORITY_LVL8 )   /* PIB (8259) */ #   define INIT_EXT_SRC1	( INT_MASK_BIT | PRIORITY_LVL0 ) /* Falcon ECC*/ #   define INIT_EXT_SRC2	( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL14 )  /* primary ethernet */ #   define INIT_EXT_SRC3	( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL0 )   /* Watchdog Timer Level 1 */#   define INIT_EXT_SRC4	( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL10 ) /* 21554 Secondary PCI Bus */#   define INIT_EXT_SRC5	( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL0 )   /* cPCI Bus INTA */ #   define INIT_EXT_SRC6	( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL0 )   /* cPCI Bus INTB */ #   define INIT_EXT_SRC7	( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL0 )   /* cPCI Bus INTC */ #   define INIT_EXT_SRC8	( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL0 )  /* cPCI bus INTD */ #   define INIT_EXT_SRC9	( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL3 )  /* PMC1A/PMC2B */ #   define INIT_EXT_SRC10	( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL3 )  /* PMC1B/PMC2C */ #   define INIT_EXT_SRC11	( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL3 )  /* PMC1C/PMC2D */ #   define INIT_EXT_SRC12	( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL3 )   /* PMC1D/PMC2A */ #   define INIT_EXT_SRC13	( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL0 )   /* not used */ #   define INIT_EXT_SRC14	( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL0 )   /* not used */ #   define INIT_EXT_SRC15	( INT_MASK_BIT | LEVEL_SENSE |\				  PRIORITY_LVL0 )   /* not used */#endif /* MCPN750 *//* * PCI autoconfiguration "roll call" list: * Each entry in the "roll call" list defined below, consists of two * separate components: a "count" component followed by a PCI header * "vendor/ID value" component.  During the first phase of PCI * autoconfiguration, the "enumeration" phase, the PCI busses are * dynamically probed and a list of devices actually found is * constructed.  After the enumeration pass is complete, the * dynamically created list of actual devices is compared against the * "roll call" list.  For each defined "device/vendor ID" in the roll * call list, the corresponding entry in the dynamically created * enumeration list is queried.  If the dynamic list indicates fewer * devices of the desired type than the "roll call" list does, the PCI * enumeration pass is performed again and a new dynamic list is * created.  This process will continue until the roll call list is * actually satisfied by devices found during dynamic enumeration or * until a timeout value (specified by ROLL_CALL_MAX_DURATION) is * exceeded.  After the enumeration phase is completed (by satisfying * the "roll call" list or by exceeding the roll call timeout), the * second phase of PCI autoconfiguration (address assignment) is * performed. *  * The roll call list is useful for holding off autoconfiguration while * devices make themselves visible on the cPCI bus. * * ROLL_CALL_MAX_DURATION defines the maximum number of seconds that * the enumeration process will run before PCI configuration proceeds.   * That is, even if the roll call repeatedly fails, the configuration  * will proceed anyway after ROLL_CALL_MAX_DURATION seconds. * * To eliminate roll call checking altogether, simply make sure that * PCI_ROLL_CALL_LIST_ENTRIES is not defined. * * The code below sets up the * roll call list to specify seven Dec21554 * devices with a roll call timeout value of 2 seconds. */#ifdef MCP750#define DEC21554_COUNT 7#define PCI_ROLL_CALL_LIST_ENTRIES \    { DEC21554_COUNT, PCI_ID_DEV_DEC21554, PCI_ID_VEND_DEC21554 },#ifdef PCI_ROLL_CALL_LIST_ENTRIES#   define ROLL_CALL_MAX_DURATION 2#endif#endif /* MCPN750 */#include "mcpx750.h"#if FALSE        /* set TRUE to include USB support *//* USB Host Components */ #   define INCLUDE_USB                  /* Main USB Component */#   undef  INCLUDE_USB_INIT             /* USB Initialization */#   define INCLUDE_UHCI                 /* UHCI Controller Driver */#   undef  INCLUDE_UHCI_INIT            /* UHCI Initialization */#   undef  INCLUDE_OHCI                 /* OHCI Controller Driver */#   undef  INCLUDE_OHCI_INIT            /* OHCI Initialization */#   undef  INCLUDE_OHCI_PCI_INIT        /* OHCI PCI Initialization */#   define INCLUDE_USBTOOL              /* usbTool Application */#   undef  INCDLUE_USB_AUDIO_DEMO       /* USB Audio Demo */#   define INCLUDE_USB_MOUSE            /* USB Mouse Driver */#   undef  INCLUDE_USB_MOUSE_INIT       /* Mouse Driver Initialization */#   define INCLUDE_USB_KEYBOARD         /* USB Keyboard Driver */#   undef  INCLUDE_USB_KEYBOARD_INIT    /* Keyboard Driver Initialization */#   define INCLUDE_USB_PRINTER          /* USB Printer Driver */#   undef  INCLUDE_USB_PRINTER_INIT     /* Printer Driver Initialization */#   define INCLUDE_USB_SPEAKER          /* USB Speaker Driver */#   undef  INCLUDE_USB_SPEAKER_INIT     /* Speaker Driver Initialization */#   undef  INCLUDE_USB_MS_BULKONLY      /* USB Bulk Driver */#   undef  INCLUDE_USB_MS_BULKONLY_INIT /* Bulk Driver Initialization */#   undef  INCLUDE_USB_MS_CBI           /* USB CBI Driver */#   undef  INCLUDE_USB_MS_CBI_INIT      /* CBI Driver Initialization */#   undef  INCLUDE_USB_PEGASUS_END      /* USB Pegasus Network Driver */#   undef  INCLUDE_USB_PEGASUS_END_INIT /* Pegaus Driver Initialization */ /*  USB Parameters */ #   define BULK_DRIVE_NAME "/bd"                /* Bulk Drive Name */#   define CBI_DRIVE_NAME "/cbid"               /* CBI Drive Name */#   define PEGASUS_IP_ADDRESS "90.0.0.3"        /* Pegasus IP Address */#   define PEGASUS_DESTINATION_ADDRESS "90.0.0.53" /* Pegasus Destination Address */#   define PEGASUS_NET_MASK 0xffffff00          /* Pegasus Net Mask */#   define PEGASUS_TARGET_NAME "host"           /* Pegasus Target Name */ #endif #ifdef __cplusplus}#endif#if defined(PRJ_BUILD)#include "prjParams.h"#endif#endif	/* INCconfigh */