/* sysALib.s - Motorola system-dependent assembly routines *//* Copyright 1984-1999 Wind River Systems, Inc. *//* Copyright 1996,1997,1998,1999 Motorola, Inc. All Rights Reserved */        .data	.globl	copyright_wind_river	.long	copyright_wind_river/*modification history--------------------02a,23may02,mil  Turned off L2 cache in sysInit (SPR #72214).01z,01nov01,mil  Use of macros for directives and function header updates.01y,08may01,pch  Add assembler abstractions (FUNC_EXPORT, FUNC_BEGIN, etc.)01x,22jan99,scb  Removed code which sets ROM_BASED flag.01w,21dec98,mas  Added setting of SIED and BHTE bits in HID0 (SPR 22955);                 added Raven3 compatibility.01v,08dec98,scb  Fixed problems with ROM_BASED flag.01u,18nov98,scb  Added global flag setting to indicate non ROM based.01t,30sep98,tm   Fixed ILOCK bit clear in MPC750 iCache enable (SPR 22121)01s,18sep98,dat  removed unnecessary sysGetDec()01r,21jul98,scb  Minor mods to define name references.01q,13jan98,srr  SPR 20104, correct use of HI and HIADJ macros01p,07jan98,rhk  Code cleanup + modified sysInit to make initialization as 		 close as possible to that in romInit.01o,15dec97,rhk  Added sysSioRead and sysSioWrite.01n,19nov97,srr  Added initial support for MCP750, sioInit changes for PC87307.01m,16oct97,scb  added routines to get L2CR, HID1 and put L2CR.01l,08oct97,srr  removed second disabling of GLANCE.01k,05nov97,mas  added eieio/sync pair to sysMemProbeSup() (SPR 9717).01j,25jul97,srr/ added 604r (Mach 5) support (SPR 8911).            mas01i,14jul97,mas  added sysMemProbeSup(), sysIn16(), sysOut16(), sysIn32(),		 sysOut32() (SPR 8022).01h,29may97,srr  Duplicate the GLANCE, RAVEN, and SIO code in sysALib.s as in		 romInit.s. Chg the RAVEN #defines to support vxMemProbe and		 replace the hard coded values with #defines.  Replace the		 isync instructions with eieio in sysPci... routines.		 (MCG MR #67, 69, 74). SPRs 8289, 8560.01g,06may97,mas  added extended VME support: 0xfef8 -> FALCON_BASE_UPPER_ADRS		 (SPR 8410).01f,24apr97,mas  added Moto support for MPIC: sysPciRead32, sysPciWrite32		 (SPR 8170).01e,11apr97,mas  added sysPciInByte, sysPciOutByte, sysPciInWord, sysPciOutWord,                 sysPciInLong, sysPciOutLong; removed doPciCSA, pciIoSync                 (SPR 8226).01d,19feb97,mas  in sysInit changed BOOT_COLD to BOOT_WARM_AUTOBOOT (SPR 8024).01c,02jan97,dat  documentation, mod history fix01b,17dec96,mas  moved sysPciIo.s contents here (SPR 7525).01a,01sep96,mot  written (mv1603/sysALib.s ver 01k)*//*DESCRIPTIONThis module contains system-dependent routines written in assemblylanguage.This module must be the first specified in the \f3ld\f1 command used tobuild the system.  The sysInit() routine is the system start-up code.*/#define _ASMLANGUAGE#include "vxWorks.h"#include "sysLib.h"#include "config.h"#include "regs.h"	#include "asm.h"	/* globals */	FUNC_EXPORT(_sysInit)		/* start of system code */	FUNC_EXPORT(sysInByte)	FUNC_EXPORT(sysOutByte)	FUNC_EXPORT(sysIn16)	FUNC_EXPORT(sysOut16)	FUNC_EXPORT(sysIn32)	FUNC_EXPORT(sysOut32)        FUNC_EXPORT(sysPciRead32)        FUNC_EXPORT(sysPciWrite32)        FUNC_EXPORT(sysPciInByte)        FUNC_EXPORT(sysPciOutByte)        FUNC_EXPORT(sysPciInWord)        FUNC_EXPORT(sysPciOutWord)        FUNC_EXPORT(sysPciInLong)        FUNC_EXPORT(sysPciOutLong)        FUNC_EXPORT(sysMemProbeSup)        FUNC_EXPORT(sysProbeExc)	FUNC_EXPORT(sysL2crPut)	FUNC_EXPORT(sysL2crGet)	FUNC_EXPORT(sysHid1Get)	FUNC_EXPORT(sysSioRead)	FUNC_EXPORT(sysSioWrite)	/* externals */	FUNC_IMPORT(usrInit)		_WRS_TEXT_SEG_START/***************************************************************************** sysInit - start after boot** SYNOPSIS* \ss* void sysInit*     (*     void*     )* \se** INCLUDE FILES: none** RETURNS: N/A** This is the system start-up entry point for VxWorks in RAM, the* first code executed after booting.  It disables interrupts, sets up* the stack, and jumps to the C routine usrInit() in usrConfig.c.** The initial stack is set to grow down from the address of sysInit().  This* stack is used only by usrInit() and is never used again.  Memory for the* stack must be accounted for when determining the system load address.** NOTE: This routine should not be called by the user.**/FUNC_BEGIN(_sysInit)	/* disable external interrupts */	xor	p0, p0, p0        mtmsr   p0                      /* clear the MSR register  */        /* Zero-out registers: r0 & SPRGs */        xor     r0,r0,r0        mtspr   272,r0        mtspr   273,r0        mtspr   274,r0        mtspr   275,r0        /*         *      Set MPU/MSR to a known state         *      Turn on FP         */        andi.   r3, r3, 0        ori     r3, r3, 0x2000        sync        mtmsr   r3        isync        /* Init the floating point control/status register */        mtfsfi  7,0x0        mtfsfi  6,0x0        mtfsfi  5,0x0        mtfsfi  4,0x0        mtfsfi  3,0x0        mtfsfi  2,0x0        mtfsfi  1,0x0        mtfsfi  0,0x0        isync        /* Initialize the floating point data registers to a known state */        bl      ifpdrValue        .long   0x3f800000      /* 1.0 */ifpdrValue:        mfspr   r3,8        lfs     f0,0(r3)        lfs     f1,0(r3)        lfs     f2,0(r3)        lfs     f3,0(r3)        lfs     f4,0(r3)        lfs     f5,0(r3)        lfs     f6,0(r3)        lfs     f7,0(r3)        lfs     f8,0(r3)        lfs     f9,0(r3)        lfs     f10,0(r3)        lfs     f11,0(r3)        lfs     f12,0(r3)        lfs     f13,0(r3)        lfs     f14,0(r3)        lfs     f15,0(r3)        lfs     f16,0(r3)        lfs     f17,0(r3)        lfs     f18,0(r3)        lfs     f19,0(r3)        lfs     f20,0(r3)        lfs     f21,0(r3)        lfs     f22,0(r3)        lfs     f23,0(r3)        lfs     f24,0(r3)        lfs     f25,0(r3)        lfs     f26,0(r3)        lfs     f27,0(r3)        lfs     f28,0(r3)        lfs     f29,0(r3)        lfs     f30,0(r3)        lfs     f31,0(r3)        sync        /*         *      Set MPU/MSR to a known state         *      Turn off FP         */        andi.   r3, r3, 0        sync        mtmsr   r3        isync        /* Init the Segment registers */        andi.   r3, r3, 0        isync        mtsr    0,r3        isync        mtsr    1,r3        isync        mtsr    2,r3        isync        mtsr    3,r3        isync        mtsr    4,r3        isync        mtsr    5,r3        isync        mtsr    6,r3        isync        mtsr    7,r3        isync        mtsr    8,r3        isync        mtsr    9,r3        isync        mtsr    10,r3        isync        mtsr    11,r3        isync        mtsr    12,r3        isync        mtsr    13,r3        isync        mtsr    14,r3        isync        mtsr    15,r3        isync        /* Turn off the GLANCE - L2 Cache */        lis     r3, HI(SYS_REG_SXCCR_A)        ori     r3, r3, LO(SYS_REG_SXCCR_A)        addis   r4, r0, 0x0        ori     r4, r4, 0x0070        stb     r4, 0x0(r3)        /* return from decrementer exceptions */        addis   p1, r0, 0x4c00        addi    p1, p1, 0x0064          /* load rfi (0x4c000064) to p1      */        stw     p1, 0x900(r0)           /* store rfi at 0x00000900          */	/* initialize the stack pointer */		lis     sp, HI(RAM_LOW_ADRS)	addi    sp, sp, LO(RAM_LOW_ADRS)	        /* Turn off data and instruction cache control bits */        mfspr   r3, HID0        isync        rlwinm  r4, r3, 0, 18, 15       /* r4 has ICE and DCE bits cleared */        sync        isync        mtspr   HID0, r4                /* HID0 = r4 */        isync        /* Get cpu type */        mfspr   r28, PVR        rlwinm  r28, r28, 16, 16, 31        /* invalidate the MPU's data/instruction caches */        lis     r3, 0x0        cmpli   0, 0, r28, CPU_TYPE_750        beq     cpuIs750        cmpli   0, 0, r28, CPU_TYPE_603        beq     cpuIs603        cmpli   0, 0, r28, CPU_TYPE_603E        beq     cpuIs603        cmpli   0, 0, r28, CPU_TYPE_603P        beq     cpuIs603        cmpli   0, 0, r28, CPU_TYPE_604R        bne     cpuNot604RcpuIs604R:        lis     r3, 0x0        mtspr   HID0, r3        /* disable the caches */        isync        ori     r4, r4, 0x0002  /* disable BTAC by setting bit 30 */cpuNot604R:        ori     r3, r3, 0x0C00          /* r3 has invalidate bits set */cpuIs603:        ori     r3, r3, 0xC000          /* r3 has enable and bits set */        or      r4, r4, r3              /* set bits */	sync	isync        mtspr   HID0, r4                /* HID0 = r4 */        andc    r4, r4, r3              /* clear bits */        isync        cmpli   0, 0, r28, CPU_TYPE_604        beq     cpuIs604        cmpli   0, 0, r28, CPU_TYPE_604E        beq     cpuIs604        cmpli   0, 0, r28, CPU_TYPE_604R        beq     cpuIs604        cmpli   0, 0, r28, CPU_TYPE_750        beq     cpuIs604        mtspr   HID0, r4        isync#ifdef USER_I_CACHE_ENABLE        b       iCacheOn603#else        b       cacheEnableDone#endifcpuIs750:        /* disable unified L2 without flushing */        mfspr   r3,1017        rlwinm  r3, r3, 0, 1,31        mtspr   1017,r3#ifdef USER_I_CACHE_ENABLE        mfspr   r3,HID0        sync        addi    r4,r0,0x0800        or      r3,r4,r3        mtspr   HID0,r3         /* set ICFI (bit 16) */        sync        andc    r3,r3,r4        mtspr   HID0,r3         /* clear ICFI (bit 16) */        sync        addi    r4,r0,-0x2001   /* Clear ILOCK (bit 18) (instr sign extends) */        and     r3,r3,r4        mtspr   HID0,r3        sync        ori     r3,r3,0x8000    /* Set ICE (bit 16) */        mtspr   HID0,r3        sync#endif        b       cacheEnableDonecpuIs604:        lis     r5, 0x0        ori     r5, r5, 0x1000        mtspr   CTR, r5loopDelay:        nop        bdnz    loopDelay        isync        mtspr   HID0, r4        isync        /* turn the Instruction cache ON */#ifdef USER_I_CACHE_ENABLE	        ori     r4, r4, 0x8800          /* set ICE & ICFI bit */        isync                           /* Synchronize for ICE enable */        b       writeR4iCacheOn603:        ori     r4, r4, 0x8800          /* set ICE & ICFI bit */        rlwinm  r3, r4, 0, 21, 19       /* clear the ICFI bit */        /*         * The setting of the instruction cache enable (ICE) bit must be         * preceded by an isync instruction to prevent the cache from being         * enabled or disabled while an instruction access is in progress.         */        isyncwriteR4:        mtspr   HID0, r4                /* Enable Instr Cache & Inval cache */        cmpli   0, 0, r28, CPU_TYPE_604        beq     cacheEnableDone        cmpli   0, 0, r28, CPU_TYPE_604E        beq     cacheEnableDone        cmpli   0, 0, r28, CPU_TYPE_604R        beq     cacheEnableDone        cmpli   0, 0, r28, CPU_TYPE_750        beq     cacheEnableDone        mtspr   HID0, r3                /* using 2 consec instructions */                                        /* PPC603 recommendation */#endifcacheEnableDone:        /* Enhance execution based on cpu type */        cmpli   0, 0, r28, CPU_TYPE_603        beq     raven3        cmpli   0, 0, r28, CPU_TYPE_603E        beq     raven3        cmpli   0, 0, r28, CPU_TYPE_603P        beq     raven3        /* enable branch history table for the 604 and 750 */        mfspr   r3, HID0        ori     r3, r3, _PPC_HID0_BHTE        cmpli   0, 0, r28, CPU_TYPE_750        beq     enhanceAll        /*         * CPU is not 750 or 603x so it must be a 604x.         * Disable sequential instruction execution (go superscalar) and         * enable branch history table for the 604.         */        ori     r3, r3, _PPC_HID0_SIEDenhanceAll:        mtspr   HID0, r3/*  * Disable Raven3's Watchdog Timers. * * Note: Both of Raven3's Watchdog timers must be disabled at powerup. * Otherwise Watchdog Timer 1 will time out in 512 msec and interrupt the  * board, Watchdog Timer 2 will time out in 576 msec and reset the board. */raven3:        lis     r3,HI(RAVEN_BASE_ADRS)        ori     r3, r3, LO(RAVEN_BASE_ADRS)        isync                                   /* synchronize */        lbz     r4,RAVEN_MPC_REVID(r3)          /* read REVID register */        eieio                                   /* synchronize */        sync                                    /* synchronize */        cmpli   0,0,r4,0x3                      /* Raven version 3 or above? */        bc      12,0,nodiswdog                  /* skip if Raven2 or lower */        addis   r4,r0,0x0000                    /* disable Watchdog Timers */        ori     r4,r4,0x0055                    /* load PATTERN_1 */        isync                                   /* synchronize */        stb     r4, RAVEN_MPC_WDT1CNTL(r3)      /* arm Watchdog Timer 1 */        eieio                                   /* synchronize */        sync                                    /* synchronize */        addis   r4,r0,0x0000                    /* load PATTERN_2 */        ori     r4,r4,0xaa0f                    /* max resolution */        isync                                   /* synchronize */        sth     r4, RAVEN_MPC_WDT1CNTL(r3)      /* disable Timer 1 */        eieio                                   /* synchronize */        sync                                    /* synchronize */        addis   r4,r0,0x0000                    /* load PATTERN_1 */        ori     r4,r4,0x0055        isync                                   /* synchronize */        stb     r4,RAVEN_MPC_WDT2CNTL(r3)       /* arm Watchdog Timer 2 */        eieio                                   /* synchronize */        sync                                    /* synchronize */        addis   r4,r0,0x0000                    /* load PATTERN_2 */        ori     r4,r4,0xaa0f                    /* max resolution */        isync                                   /* synchronize */        sth     r4,RAVEN_MPC_WDT2CNTL(r3)       /* disable Timer2 */        eieio                                   /* synchronize */        sync                                    /* synchronize */nodiswdog:	/* disable instruction and data translations in the MMU */	sync	mfmsr	r3			/* get the value in msr *					/* clear bits IR and DR */		rlwinm	r4, r3, 0, _PPC_MSR_BIT_DR+1, _PPC_MSR_BIT_IR - 1		mtmsr	r4			/* set the msr */	sync				/* SYNC */	/* initialize the BAT register */	li	p3,0	 		/* clear p0 */		isync	mtspr	IBAT0U,p3		/* SPR 528 (IBAT0U) */	isync	mtspr	IBAT0L,p3		/* SPR 529 (IBAT0L) */	isync	mtspr	IBAT1U,p3		/* SPR 530 (IBAT1U) */	isync	mtspr	IBAT1L,p3		/* SPR 531 (IBAT1L) */	isync	mtspr	IBAT2U,p3		/* SPR 532 (IBAT2U) */	isync	mtspr	IBAT2L,p3		/* SPR 533 (IBAT2L) */	isync	mtspr	IBAT3U,p3		/* SPR 534 (IBAT3U) */	isync	mtspr	IBAT3L,p3		/* SPR 535 (IBAT3L) */	isync	mtspr	DBAT0U,p3		/* SPR 536 (DBAT0U) */	isync	mtspr	DBAT0L,p3		/* SPR 537 (DBAT0L) */	isync	mtspr	DBAT1U,p3		/* SPR 538 (DBAT1U) */	isync	mtspr	DBAT1L,p3		/* SPR 539 (DBAT1L) */	isync	mtspr	DBAT2U,p3		/* SPR 540 (DBAT2U) */	isync	mtspr	DBAT2L,p3		/* SPR 541 (DBAT2L) */	isync	mtspr	DBAT3U,p3		/* SPR 542 (DBAT3U) */	isync	mtspr	DBAT3L,p3		/* SPR 543 (DBAT3L) */	isync	/* invalidate entries within both TLBs */	li	p1,128	xor	p0,p0,p0		/* p0 = 0    */	mtctr	p1			/* CTR = 32  */	isync				/* context sync req'd before tlbie */sysALoop:	tlbie	p0	addi	p0,p0,0x1000		/* increment bits 15-19 */	bdnz	sysALoop		/* decrement CTR, branch if CTR != 0 */	sync				/* sync instr req'd after tlbie      */	/* initialize Small Data Area (SDA) start address */#if	FALSE				/* XXX TPR NO SDA for now */	lis     r2, HI(_SDA2_BASE_)	addi    r2, r2, LO(_SDA2_BASE_)	lis     r13, HI(_SDA_BASE_)	addi    r13, r13, LO(_SDA_BASE_)#endif	addi	sp, sp, -FRAMEBASESZ	/* get frame stack */	li      r3, BOOT_WARM_AUTOBOOT	b	usrInit			/* never returns - starts up kernel */FUNC_END(_sysInit)/***************************************************************************** sysInByte - reads a byte from an address.** This function reads a byte from a specified address.** RETURNS: byte read from address** From a C point of view, the routine is defined as follows:UINT8 sysInByte    (    ULONG * addr 	/@ address of data @/    )* NOMANUAL*/FUNC_BEGIN(sysInByte)	/*	Read byte from given address */	lbzx	r3,r0,r3	/*	Sync I/O operation */	eieio	/*	Return to caller */	bclr	20,0FUNC_END(sysInByte)/***************************************************************************** sysOutByte - writes a byte to an address.** This function writes a byte to a specified address.