eieio					/* synchronize */	sync					/* synchronize */	addis	r4,r0,0x0000			/* load PATTERN_1 */	ori	r4,r4,0x0055	isync					/* synchronize */	stb	r4,RAVEN_MPC_WDT2CNTL(r3)	/* arm Watchdog Timer 2 */	eieio					/* synchronize */	sync					/* synchronize */	addis	r4,r0,0x0000			/* load PATTERN_2 */	ori	r4,r4,0xaa0f			/* max resolution */	isync					/* synchronize */	sth	r4,RAVEN_MPC_WDT2CNTL(r3)	/* disable Timer2 */	eieio					/* synchronize */	sync					/* synchronize */nodiswdog:/*# 	DRAM Initialization/Sizing for FALCON Module#	Initialize the FALCON (DRAM Controller) registers.#	The registers are initialized with values from the#	results of the probe (see below).##	algorithm:##	Each memory bank size that is possible is tried.  This starts#	with the largest to the smallest.   A table is used to inform#	the sizing code of the needed information.  The information#	consists of the memory bank size, probe addresses, and the data#	pattern associated with each of the probe address.  All off the#	probe addresses are written to first with associative write data#	pattern, then they are read.  An exact match of the data is#	required to deem the memory bank size has been found.##	Size			Key Address Lines#	40000000 (1GB)		A2#	10000000 (256MB)	A4/A6#	08000000 (128MB)	A5/A6/A18#	04000000 (64MB)		A6/A18#	02000000 (32MB)		A7/A18/A19#	01000000 (16MB)		N/A##	As you can see, this algorithm is coupled very tightly with the#	H/W, if it ever changes, this algorithm will need to be modified.##	register-usage:#		r1	= SP (not modified)#		r2	= TOC (not modified)#		r4	= DRAM attributes register address#		r5	= DRAM base-address register address#		r6	= test pattern's table pointer#		r7	= DRAM bank index (0 to 3)#		r8-r10,r12-r19	= run-time (scratch)#		r20	= saved return instruction pointer#		r21	= verify error flag#		r22	= FALCON base address#		r23	= run-time (scratch)#		r24	= VxWorks startType#		r25	= size of DRAM in bytes#*/	.set	NBANKS,4		/* number of DRAM banks */	addis	r0,r0,0			/* insure r0 is zero */	ori	r0,r0,0			/* insure r0 is zero */	or	r3,r0,r0		/* set to no memory present state */	mfspr	r20,8			/* save return instruction pointer */	bl	.falcon_i_ra		/* branch around tables */	/* DRAM controller register addresses table */	.long	FALCON_BASE_ADRS	.long	DRAM_REG_BASE		/* DRAM base-address register addr */	.long	DRAM_REG_SIZE		/* DRAM attributes register address */.falcon_i_ra:	mfspr	r4,8			/* load pointer to table */	/* load register address values */	lwz	r8,0x00(r4)		/* FALCON register base address */	lwz	r5,0x04(r4)		/* DRAM base-address register address */	lwz	r4,0x08(r4)		/* DRAM attributes register address */	or	r22,r8,r8		/* save it for later use */	eieio				/* synchronize the data stream */	sync				/* synchronize the data stream */#ifndef	INCLUDE_I2C	/* initialize to DRAM control registers to its working state */ 	bl	sysGetDramSpd		/* get RAM spd0/1 bits in r3 */	lis	r9, HI(SYS_REG_MCR_)	/* load address of Mem Config Reg */	ori	r9, r9, LO(SYS_REG_MCR_)	lwz	r9,0(r9)		/* read Memory Configuration Register */	eieio				/* data synchronize */	sync				/* data synchronize */	rlwinm	r9,r9,7,28,28 		/* mask off all but the M_FREF bit */	or	r9,r3,r9		/* IHEN=0,ADIS=0,RFREF=M_FREF */	stw	r9,0x08(r8)		/* general control register */	eieio				/* synchronize the data stream */	sync				/* synchronize the data stream */#else/* *	Temporarily force DRAM controller to use fastest refresh *	and slowest DRAM speed.  This will allow us to use the *	DRAM in an un-optimized fashion.  Now, we are capable *	of using the stack. * */	addis	r9,r0,0x0000		/* ISA_HOLE=0,ADIS=0,RFREF=1,RSPD=00 */	ori	r9,r9,0x0008	stw	r9,0x08(r8)		/* Update Falcon's general cntrl reg */	eieio				/* synchronize the data stream */	sync#endif	/* INCLUDE_I2C */        bl	sysGetBusSpd		/* get bus speed in MHZ, r3 has value */	slwi	r3,r3,24		/* move to upper byte */	stw	r3,0x20(r8)		/* CLK frequency register */	eieio				/* synchronize the data stream */	sync				/* synchronize the data stream */	/*	 * Restore r0 to zero.  The original Falcon init code relied on	 * r0 being zero.  Since then, new code which made subroutine calls	 * have been added.  These subroutines use r0 as a volatile register.	 * This is the last call before r0 is used as a zero; however, any	 * usage of a volatile register as a permanent storage location	 * is not a good idea.	 */	addis	r0,r0,0			/* insure r0 is zero */	ori	r0,r0,0			/* insure r0 is zero */	addis	r9,r0,0x0000		/* SWEN=0,RTEST=000 */	ori	r9,r9,0x0000		/* SWEN=0,RTEST=000 */	stw	r9,0x40(r8)		/* DRAM scrub/refresh register */	eieio				/* synchronize the data stream */	sync				/* synchronize the data stream */	addis	r9,r0,0x0100		/* RWCB=0,DERC=1,xIEN=0,MCKEN=0 */	ori	r9,r9,0x0000		/* RWCB=0,DERC=1,xIEN=0,MCKEN=0 */	stw	r9,0x28(r8)		/* DRAM ECC control register */	eieio				/* synchronize the data stream */	sync				/* synchronize the data stream */	addis	r9,r0,0x8000		/* ELOG=1,ESEN=0,SCOF=1 */	ori	r9,r9,0x0100		/* ELOG=1,ESEN=0,SCOF=1 */	stw	r9,0x30(r8)		/* DRAM ECC error-logger register */	eieio				/* synchronize the data stream */	sync				/* synchronize the data stream */	bl	.falcon_i_tp		/* branch around tables */	/* write-addresses/data-patterns table (address/hi-data/lo-data) */	.set	DRAM_SIZE1,0		/* size index */	.set	DRAM_ATTR1,4		/* attributes index */	.set	DRAM_CHCK1,8		/* address/pattern starting index */	.set	TBLEND,-1		/* table end marker */	/* 1GB */	.long	0x40000000,0x06	.long	0x00000000,0x01010101,0xFEFEFEFE	.long	0x20000000,0x02020202,0xFDFDFDFD	.long	-1					/* table entry end */	/* 256MB */	.long	0x10000000,0x05	.long	0x00000000,0x03030303,0xFCFCFCFC	.long	0x02000000,0x04040404,0xFBFBFBFB	.long	0x08000000,0x05050505,0xFAFAFAFA	.long	0x0A000000,0x06060606,0xF9F9F9F9	.long	-1					/* table entry end */	/* 128MB */	.long	0x08000000,0x04	.long	0x00000000,0x07070707,0xF8F8F8F8	.long	0x00002000,0x08080808,0xF7F7F7F7	.long	0x02000000,0x09090909,0xF6F6F6F6	.long	0x02002000,0x0A0A0A0A,0xF5F5F5F5	.long	0x04000000,0x0B0B0B0B,0xF4F4F4F4	.long	0x04002000,0x0C0C0C0C,0xF3F3F3F3	.long	0x06000000,0x0D0D0D0D,0xF2F2F2F2	.long	0x06002000,0x0E0E0E0E,0xF1F1F1F1	.long	-1					/* table entry end */	/* 64MB */	.long	0x04000000,0x03	.long	0x00000000,0x0F0F0F0F,0xF0F0F0F0	.long	0x00002000,0x10101010,0xEFEFEFEF	.long	0x02000000,0x11111111,0xEEEEEEEE	.long	0x02002000,0x12121212,0xEDEDEDED	.long	-1					/* table entry end */	/* 32MB */	.long	0x02000000,0x02	.long	0x00000000,0x13131313,0xECECECEC	.long	0x00001000,0x14141414,0xEBEBEBEB	.long	0x00002000,0x15151515,0xEAEAEAEA	.long	0x00003000,0x16161616,0xE9E9E9E9	.long	0x01000000,0x17171717,0xE8E8E8E8	.long	0x01001000,0x18181818,0xE7E7E7E7	.long	0x01002000,0x19191919,0xE6E6E6E6	.long	0x01003000,0x1A1A1A1A,0xE5E5E5E5	.long	-1					/* table entry end */	/* 16MB */	.long	0x01000000,0x01	.long	0x00000000,0x1B1B1B1B,0xE4E4E4E4        /* pattern at address 0x1000 is not needed to detect 16MB           presence per Hawk algorithm, but is added to address           data bus capacitance on some boards when bank is empty         */	.long	0x00001000,0x1C1C1C1C,0xE3E3E3E3        /* bus capacitance */	.long	-1					/* table entry end */	.long	-1					/* table end */.falcon_i_tp:	mfspr	r6,8			/* load pointer to table *//* *	disable all DRAM banks and set to "block not present" size *	set all DRAM banks base-address register to zero */	addi	r7,r0,0			/* clear DRAM bank index register */	addi	r8,r0,0x00		/* disable and set to no-size */.falcon_i_ks:	stbx	r8,r7,r4		/* write DRAM attributes register */	stbx	r0,r7,r5		/* write DRAM bank base-address reg */	addi	r7,r7,1			/* increment bank index */	cmpli	0,0,r7,NBANKS		/* are we done yet? */	bc	4,2,.falcon_i_ks	/* if not equal, no, branch *//* *	probe for the existance of all possible DRAM banks * *	on a DRAM bank basis, the DRAM bank is enabled with the size *	as specified by the current table entry, then perform the data *	writes at the specified addresses as specified by the current table *	entry, then read and verify the locations written with the *	expected data * *	following each probe the DRAM bank will be disabled, if the DRAM *	bank is present, its attributes register will be initialized to *	the size found (i.e., size-encoding bits set to proper state) */	addi	r23,r0,TBLEND		/* setup table end indicator */	addi	r7,r0,0			/* clear DRAM bank index register */.falcon_i_pp:	or	r19,r6,r6		/* copy pointer to table */	or	r10,r6,r6		/* copy pointer to table */	/* write test data patterns (as specified by the current table entry) */.falcon_i_pp_i:	or	r19,r10,r10		/* copy current table entry pointer */	addi	r21,r0,0		/* clear verify error flag */	lwz	r14,DRAM_ATTR1(r10)	/* load DRAM attributes(encoded size)*/	ori	r14,r14,0x80		/* set bank enable bit */	stbx	r14,r7,r4		/* write DRAM attributes register */	eieio				/* data synchronize */	sync				/* data synchronize */	addi	r10,r10,DRAM_CHCK1	/* move pointer to data patterns */.falcon_i_pp_w:	lwz	r12,0(r10)		/* load write data pattern address */	lwz	r13,4(r10)		/* load write data pattern hi */	lwz	r14,8(r10)		/* load write data pattern lo */	eieio				/* data synchronize */	sync				/* data synchronize */	stw	r13,0(r12)		/* write data pattern hi */	eieio				/* data synchronize */	sync				/* data synchronize */	stw	r14,4(r12)		/* write data pattern lo */	eieio				/* data synchronize */	sync				/* data synchronize */	addi	r10,r10,12		/* increment to next address */	lwz	r12,0(r10)		/* load write data pattern address */	cmpl	0,0,r12,r23		/* check for table entry end */	bc	4,2,.falcon_i_pp_w	/* if not equal, no, branch */	or	r10,r19,r19		/* copy current table entry pointer */	addi	r10,r10,DRAM_CHCK1	/* move pointer to data patterns */.falcon_i_pp_r:	lwz	r12,0(r10)		/* load write data pattern address */	lwz	r13,4(r10)		/* load write data pattern hi */	lwz	r14,8(r10)		/* load write data pattern lo */	eieio				/* data synchronize */	sync				/* data synchronize */	lwz	r15,0(r12)		/* read data pattern hi */	eieio				/* data synchronize */	sync				/* data synchronize */	lwz	r16,4(r12)		/* read data pattern lo */	eieio				/* data synchronize */	sync				/* data synchronize */	cmpl	0,0,r13,r15		/* do they verify? */	bc	4,2,.falcon_i_pp_f	/* if not equal, no, branch */	cmpl	0,0,r14,r16		/* do they verify? */	bc	4,2,.falcon_i_pp_f	/* if not equal, no, branch */	b	.falcon_i_pp_p		/* verification passed */.falcon_i_pp_f:	addi	r21,r21,1		/* increment verify error flag */.falcon_i_pp_p:	addi	r10,r10,12		/* increment to next address */	lwz	r12,0(r10)		/* load write data pattern address */	cmpl	0,0,r12,r23		/* check for table entry end */	bc	4,2,.falcon_i_pp_r	/* if not equal, no, branch */	addi	r10,r10,4		/* increment to one pass the end */	cmpli	0,0,r21,0		/* any errors? */	bc	4,2,.falcon_i_pp_d	/* if not equal, yes, branch */	lbzx	r8,r7,r4		/* read DRAM attributes register */	eieio				/* data synchronize */	sync				/* data synchronize */	andi.	r8,r8,0x7F		/* mask off the bank enable bit */	stbx	r8,r7,r4		/* write DRAM attributes register */	eieio				/* data synchronize */	sync				/* data synchronize */	b	.falcon_i_pp_n		/* branch to bank by bank loop control*/.falcon_i_pp_d:	addi	r8,r0,0x00		/* disable and set to no-size */	stbx	r8,r7,r4		/* write DRAM attributes register */	eieio				/* data synchronize */	sync				/* data synchronize */	lwz	r12,0(r10)		/* load write data pattern address */	cmpl	0,0,r12,r23		/* check for table end */	bc	4,2,.falcon_i_pp_i	/* if not equal, no, branch */.falcon_i_pp_n:	addi	r7,r7,1			/* increment bank index */	cmpli	0,0,r7,NBANKS		/* are we done yet? */	bc	4,2,.falcon_i_pp	/* if not equal, no, branch *//* *	at this point the DRAM bank attributes registers will be initialized *	to the size-encoding of the DRAM which is present (i.e., probed), *	else the DRAM attributes registers contain zero indicating no DRAM *	was found * *	the DRAM that was found must be aligned to a boundary of its size * *	the following code will begin allocating memory address spaces *	starting with the largest first, and working itself to the *	smallest * *	memory will start address zero */	bl	.falcon_i_tp_s		/* branch around tables */	.long	0x40000000,0x00000006	/* 1024MB */	.long	0x10000000,0x00000005	/* 256MB */	.long	0x08000000,0x00000004	/* 128MB */	.long	0x04000000,0x00000003	/* 64MB */	.long	0x02000000,0x00000002	/* 32MB */	.long	0x01000000,0x00000001	/* 16MB */	.long	TBLEND			/* table entry end */.falcon_i_tp_s:	mfspr	r6,8			/* load pointer to table */	or	r10,r6,r6		/* copy table pointer */	addi	r23,r0,TBLEND		/* setup table end indicator */	addi	r25,r0,0		/* clear table index counter */	or	r13,r0,r0		/* memory base address (zero) */.falcon_i_sz:	addi	r7,r0,0			/* clear DRAM bank index register */	lwz	r8,DRAM_ATTR1(r10)	/* load DRAM attributes for this entry*/.falcon_i_sz_b:	lbzx	r9,r7,r4		/* read DRAM attributes register */	andi.	r9,r9,0x7		/* mask off unwanted data bits */	cmpl	0,0,r8,r9		/* do the attributes match? */	bc	4,2,.falcon_i_sz_no	/* if not equal, no, branch */	rlwinm	r9,r13,8,8,31		/* extract PowerPC A0-A7 bits */	stbx	r9,r7,r5		/* write DRAM bank base-address reg */	eieio				/* data synchronize */	sync				/* data synchronize */	lbzx	r9,r7,r4		/* read DRAM attributes register */	ori	r9,r9,0x80		/* set bank enable bit */	stbx	r9,r7,r4		/* write DRAM attributes register */	eieio				/* data synchronize */	sync				/* data synchronize */	lwz	r9,DRAM_SIZE1(r10)	/* load DRAM size for this entry */	add	r25,r25,r9		/* add to the total DRAM size */	add	r13,r13,r9		/* add it to the memory base address */.falcon_i_sz_no:	addi	r7,r7,1			/* increment bank index */	cmpli	0,0,r7,NBANKS		/* are we done yet? */	bc	4,2,.falcon_i_sz_b	/* if not equal, no, branch */	addi	r10,r10,8		/* increment to next table entry */	lwz	r14,0(r10)		/* load memory size variable */	cmpl	0,0,r14,r23		/* check for table end */	bc	4,2,.falcon_i_sz	/* if not equal, no, branch */	/* r25 now contains the total DRAM size (in bytes) */	/* work-around for a scrubber/refresh logic bug */	lwz	r4,0x10(r22)		/* copy the bank enables/sizes reg */	eieio				/* data synchronize */	sync				/* data synchronize */	addis	r5,r0,0			/* gimme a zero */	stw	r5,0x10(r22)		/* disable all, set sizes to zero */	eieio				/* data synchronize */	sync				/* data synchronize */