(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2004 7 9 17 15 35)
   (author "Xilinx, Inc.")
   (program "ChipScope Pro Core Generator" (version "6.2.03i (build 4.141.1079)"))))
   (comment "**********************************")
   (comment "Component name: icon_pro")
   (comment "Device family: Spartan2")
   (comment "Control port count: 2")
   (comment "Enable BSCAN instance: true")
   (comment "BSCAN chain: USER1")
   (comment "Enable JTAG global clock buffer: true")
   (comment "Enable unused BSCAN ports: false")
   (comment "Force RPM Grid Usage: no")
   (comment "**********************************")
   (comment "                                                                                
      This file is owned and controlled by Xilinx and must be used              
      solely for design, simulation, implementation and creation of             
      design files limited to Xilinx devices or technologies. Use               
      with non-Xilinx devices or technologies is expressly prohibited           
      and immediately terminates your license.                                  
                                                                                
      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'             
      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                   
      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION           
      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION               
      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                 
      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                   
      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE          
      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                  
      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                   
      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR            
      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF           
      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS           
      FOR A PARTICULAR PURPOSE.                                                 
                                                                                
      Xilinx products are not intended for use in life support                  
      appliances, devices, or systems. Use in such applications are             
      expressly prohibited.                                                     
                                                                                
      (c) Copyright 1995-2003 Xilinx, Inc.                                      
      All rights reserved.                                                      
                                                                                
   ")
   (comment "Core parameters: ")
       (comment "c_use_control2 = 0 ")
       (comment "c_use_control1 = 1 ")
       (comment "c_user_scan_chain = 1 ")
       (comment "c_use_control0 = 1 ")
       (comment "c_major_version = 6 ")
       (comment "c_core_type = 1 ")
       (comment "c_device_family = 4 ")
       (comment "c_use_ext_bscan = 0 ")
       (comment "c_num_control_ports = 2 ")
       (comment "c_use_jtag_bufg = 1 ")
       (comment "c_mfg_id = 1 ")
       (comment "InstanceName = icon_pro ")
       (comment "c_use_control14 = 0 ")
       (comment "c_use_control13 = 0 ")
       (comment "c_use_control12 = 0 ")
       (comment "c_use_control11 = 0 ")
       (comment "c_use_control10 = 0 ")
       (comment "c_use_unused_bscan = 0 ")
       (comment "c_use_control9 = 0 ")
       (comment "c_minor_version = 2 ")
       (comment "c_use_control8 = 0 ")
       (comment "c_use_control7 = 0 ")
       (comment "c_use_control6 = 0 ")
       (comment "c_use_control5 = 0 ")
       (comment "c_use_control4 = 0 ")
       (comment "c_build_revision = 2 ")
       (comment "c_use_control3 = 0 ")
   (external xilinxun (edifLevel 0)
      (technology (numberDefinition))
       (cell VCC (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port P (direction OUTPUT))
               )
           )
       )
       (cell GND (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port G (direction OUTPUT))
               )
           )
       )
       (cell BSCAN_VIRTEX (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port RESET (direction OUTPUT))
                   (port UPDATE (direction OUTPUT))
                   (port SHIFT (direction OUTPUT))
                   (port DRCK1 (direction OUTPUT))
                   (port DRCK2 (direction OUTPUT))
                   (port SEL1 (direction OUTPUT))
                   (port SEL2 (direction OUTPUT))
                   (port TDI (direction OUTPUT))
                   (port TDO1 (direction INPUT))
                   (port TDO2 (direction INPUT))
               )
           )
       )
       (cell BUFG (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port I (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell FDC (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port C (direction INPUT))
                   (port CLR (direction INPUT))
                   (port Q (direction OUTPUT))
               )
           )
       )
       (cell FDCE (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port C (direction INPUT))
                   (port CE (direction INPUT))
                   (port CLR (direction INPUT))
                   (port Q (direction OUTPUT))
               )
           )
       )
       (cell FDE (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port C (direction INPUT))
                   (port CE (direction INPUT))
                   (port Q (direction OUTPUT))
               )
           )
       )
       (cell FDR (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port C (direction INPUT))
                   (port R (direction INPUT))
                   (port Q (direction OUTPUT))
               )
           )
       )
       (cell FDRE (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port C (direction INPUT))
                   (port CE (direction INPUT))
                   (port R (direction INPUT))
                   (port Q (direction OUTPUT))
               )
           )
       )
       (cell INV (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port I (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell LUT1 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port I0 (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell LUT2 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port I0 (direction INPUT))
                   (port I1 (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell LUT3 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port I0 (direction INPUT))
                   (port I1 (direction INPUT))
                   (port I2 (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell LUT4 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port I0 (direction INPUT))
                   (port I1 (direction INPUT))
                   (port I2 (direction INPUT))
                   (port I3 (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell MUXCY_L (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port DI (direction INPUT))
                   (port CI (direction INPUT))
                   (port S (direction INPUT))
                   (port LO (direction OUTPUT))
               )
           )
       )
       (cell MUXF5 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port I0 (direction INPUT))
                   (port I1 (direction INPUT))
                   (port S (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell MUXF6 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port I0 (direction INPUT))
                   (port I1 (direction INPUT))
                   (port S (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell XORCY (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port LI (direction INPUT))
                   (port CI (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
   )
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell icon_pro
 (cellType GENERIC) (view view_1 (viewType NETLIST)
  (interface
   (port ( rename control0_35_ "control0<35>") (direction INOUT))
   (port ( rename control0_34_ "control0<34>") (direction INOUT))
   (port ( rename control0_33_ "control0<33>") (direction INOUT))
   (port ( rename control0_32_ "control0<32>") (direction INOUT))
   (port ( rename control0_31_ "control0<31>") (direction INOUT))
   (port ( rename control0_30_ "control0<30>") (direction INOUT))
   (port ( rename control0_29_ "control0<29>") (direction INOUT))
   (port ( rename control0_28_ "control0<28>") (direction INOUT))
   (port ( rename control0_27_ "control0<27>") (direction INOUT))
   (port ( rename control0_26_ "control0<26>") (direction INOUT))
   (port ( rename control0_25_ "control0<25>") (direction INOUT))
   (port ( rename control0_24_ "control0<24>") (direction INOUT))