(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2004 7 9 17 15 38)
   (author "Xilinx, Inc.")
   (program "ChipScope Pro Core Generator" (version "6.2.03i (build 4.141.1079)"))))
   (comment "**********************************")
   (comment "Creating EDIF Netlistila_pro_1.edn")
   (comment "Component Name: ila_pro_1")
   (comment "Core Version: v6.2.2")
   (comment "Device Family: Spartan2")
   (comment "SRL16 Type: SRL16/E")
   (comment "RAM Type: 4096-bit block RAM")
   (comment "Clock Edge Used for Sampling: rising edge")
   (comment "RPM Usage: disabled")
   (comment "Trigger Output Port: disabled")
   (comment "Data Same as Trigger: true")
   (comment "  Data port is made up of the following trigger ports:")
   (comment "    Trigger Port 0")
   (comment "Aggregate Data Width: 8")
   (comment "Data Depth: 256")
   (comment "Enable Gap Recording: false")
   (comment "Enable Timestamp Recording: false")
   (comment "Number of Trigger Ports: 1")
   (comment "  Trigger Port 0 Width:8")
   (comment "Number of Match Units: 1")
   (comment "  Match Unit 0 Info:")
   (comment "    Connection: Trigger Port 0")
   (comment "    Type: Basic")
   (comment "    Match Counter : disabled")
   (comment "Trigger Sequencer Type : Basic")
   (comment "  Number of trigger sequencer levels: 16")
   (comment "External capture : disabled")
   (comment "Force RPM Grid Usage: no")
   (comment "**********************************")
   (comment "                                                                                
      This file is owned and controlled by Xilinx and must be used              
      solely for design, simulation, implementation and creation of             
      design files limited to Xilinx devices or technologies. Use               
      with non-Xilinx devices or technologies is expressly prohibited           
      and immediately terminates your license.                                  
                                                                                
      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'             
      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                   
      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION           
      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION               
      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                 
      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                   
      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE          
      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                  
      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                   
      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR            
      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF           
      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS           
      FOR A PARTICULAR PURPOSE.                                                 
                                                                                
      Xilinx products are not intended for use in life support                  
      appliances, devices, or systems. Use in such applications are             
      expressly prohibited.                                                     
                                                                                
      (c) Copyright 1995-2003 Xilinx, Inc.                                      
      All rights reserved.                                                      
                                                                                
   ")
   (comment "Core parameters: ")
       (comment "c_use_trigdata15 = 0 ")
       (comment "c_trig14_width = 1 ")
       (comment "c_use_trigdata14 = 0 ")
       (comment "c_use_trigdata13 = 0 ")
       (comment "c_use_trigdata12 = 0 ")
       (comment "c_use_trigdata11 = 0 ")
       (comment "c_trig15_width = 1 ")
       (comment "c_use_trigdata10 = 0 ")
       (comment "c_m13_type = 1 ")
       (comment "c_use_trig9 = 0 ")
       (comment "c_use_trig8 = 0 ")
       (comment "c_use_trig7 = 0 ")
       (comment "c_use_trig6 = 0 ")
       (comment "c_use_trig5 = 0 ")
       (comment "c_trig11_width = 1 ")
       (comment "c_use_trig4 = 0 ")
       (comment "c_use_trig3 = 0 ")
       (comment "c_use_trig2 = 0 ")
       (comment "c_use_trig1 = 0 ")
       (comment "c_trig12_width = 1 ")
       (comment "c_use_trig0 = 1 ")
       (comment "c_ext_cap_use_reg = 1 ")
       (comment "c_num_ext_cap_pins = 20 ")
       (comment "c_m3_tpid = 1 ")
       (comment "c_mfg_id = 1 ")
       (comment "c_trig10_width = 1 ")
       (comment "c_trig8_width = 1 ")
       (comment "c_m7_tpid = 1 ")
       (comment "c_trig9_width = 1 ")
       (comment "c_use_mcnt9 = 0 ")
       (comment "c_use_mcnt8 = 0 ")
       (comment "c_use_mcnt7 = 0 ")
       (comment "c_major_version = 6 ")
       (comment "c_use_mcnt6 = 0 ")
       (comment "c_m0_type = 0 ")
       (comment "c_use_mcnt5 = 0 ")
       (comment "c_trig5_width = 1 ")
       (comment "c_use_mcnt4 = 0 ")
       (comment "c_num_match_units = 1 ")
       (comment "c_use_mcnt3 = 0 ")
       (comment "c_m13_tpid = 1 ")
       (comment "c_use_mcnt2 = 0 ")
       (comment "c_use_mcnt1 = 0 ")
       (comment "c_use_mcnt0 = 0 ")
       (comment "c_trig6_width = 1 ")
       (comment "c_trig7_width = 1 ")
       (comment "c_m4_type = 1 ")
       (comment "c_trig3_width = 1 ")
       (comment "c_m8_type = 1 ")
       (comment "c_trig4_width = 1 ")
       (comment "c_m10_type = 1 ")
       (comment "c_num_tseq_states = 16 ")
       (comment "c_trig0_width = 8 ")
       (comment "c_m14_type = 1 ")
       (comment "c_use_data = 0 ")
       (comment "c_trig1_width = 1 ")
       (comment "c_trig2_width = 1 ")
       (comment "c_m0_tpid = 0 ")
       (comment "c_timestamp_width = 32 ")
       (comment "c_data_depth = 256 ")
       (comment "c_ram_type = 0 ")
       (comment "c_use_gap = 0 ")
       (comment "c_m4_tpid = 1 ")
       (comment "c_use_trig_out = 0 ")
       (comment "c_m8_tpid = 1 ")
       (comment "c_m10_tpid = 1 ")
       (comment "c_num_tseq_cnt = 0 ")
       (comment "c_m1_type = 1 ")
       (comment "c_m14_tpid = 1 ")
       (comment "c_timestamp_type = 0 ")
       (comment "c_m5_type = 1 ")
       (comment "c_m9_type = 1 ")
       (comment "c_m11_type = 1 ")
       (comment "c_tseq_cnt0_width = 1 ")
       (comment "c_tseq_cnt1_width = 1 ")
       (comment "c_m15_type = 0 ")
       (comment "c_use_rpm = 0 ")
       (comment "c_m1_tpid = 1 ")
       (comment "c_mcnt9_width = 1 ")
       (comment "c_m5_tpid = 1 ")
       (comment "c_core_type = 2 ")
       (comment "c_use_atc_clkin = 0 ")
       (comment "c_ext_cap_pin_mode = 0 ")
       (comment "c_ext_cap_rate_mode = 0 ")
       (comment "c_use_inv_clk = 0 ")
       (comment "c_m9_tpid = 1 ")
       (comment "c_m11_tpid = 1 ")
       (comment "c_mcnt6_width = 1 ")
       (comment "c_minor_version = 2 ")
       (comment "c_use_trigdata9 = 0 ")
       (comment "c_use_trigdata8 = 0 ")
       (comment "c_use_trigdata7 = 0 ")
       (comment "c_mcnt7_width = 1 ")
       (comment "c_use_trigdata6 = 0 ")
       (comment "c_use_trigdata5 = 0 ")
       (comment "c_use_trigdata4 = 0 ")
       (comment "c_use_trigdata3 = 0 ")
       (comment "c_use_trigdata2 = 0 ")
       (comment "c_mcnt8_width = 1 ")
       (comment "c_m2_type = 1 ")
       (comment "c_use_trigdata1 = 0 ")
       (comment "c_use_trigdata0 = 1 ")
       (comment "c_m15_tpid = 0 ")
       (comment "c_tseq_type = 1 ")
       (comment "c_timestamp_depth = 512 ")
       (comment "c_mcnt4_width = 1 ")
       (comment "c_m6_type = 1 ")
       (comment "c_mcnt5_width = 1 ")
       (comment "c_device_family = 4 ")
       (comment "c_mcnt1_width = 1 ")
       (comment "c_m12_type = 1 ")
       (comment "c_mcnt14_width = 1 ")
       (comment "c_mcnt2_width = 1 ")
       (comment "c_mcnt15_width = 1 ")
       (comment "c_tc_mcnt_width = 1 ")
       (comment "c_mcnt3_width = 1 ")
       (comment "c_use_mcnt15 = 0 ")
       (comment "c_use_mcnt14 = 0 ")
       (comment "c_mcnt11_width = 1 ")
       (comment "c_use_mcnt13 = 0 ")
       (comment "c_use_mcnt12 = 0 ")
       (comment "c_use_mcnt11 = 0 ")
       (comment "c_use_mcnt10 = 0 ")
       (comment "c_mcnt12_width = 1 ")
       (comment "c_mcnt0_width = 1 ")
       (comment "c_m2_tpid = 1 ")
       (comment "c_mcnt13_width = 1 ")
       (comment "c_use_tc_mcnt = 0 ")
       (comment "InstanceName = ila_pro_1 ")
       (comment "c_m6_tpid = 1 ")
       (comment "c_mcnt10_width = 1 ")
       (comment "c_m12_tpid = 1 ")
       (comment "c_use_trig15 = 0 ")
       (comment "c_use_trig14 = 0 ")
       (comment "c_srl16_type = 1 ")
       (comment "c_use_trig13 = 0 ")
       (comment "c_use_trig12 = 0 ")
       (comment "c_use_trig11 = 0 ")
       (comment "c_use_trig10 = 0 ")
       (comment "c_m3_type = 1 ")
       (comment "c_data_width = 1 ")
       (comment "c_m7_type = 1 ")
       (comment "c_build_revision = 2 ")
       (comment "c_trig13_width = 1 ")
   (external xilinxun (edifLevel 0)
      (technology (numberDefinition))
       (cell VCC (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port P (direction OUTPUT))
               )
           )
       )
       (cell GND (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port G (direction OUTPUT))
               )
           )
       )
       (cell FDCE (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port C (direction INPUT))
                   (port CE (direction INPUT))
                   (port CLR (direction INPUT))
                   (port Q (direction OUTPUT))
               )