?? ila_pro_1.edn
字號:
)
)
(cell FDCP (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port D (direction INPUT))
(port C (direction INPUT))
(port CLR (direction INPUT))
(port PRE (direction INPUT))
(port Q (direction OUTPUT))
)
)
)
(cell FDE (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port D (direction INPUT))
(port C (direction INPUT))
(port CE (direction INPUT))
(port Q (direction OUTPUT))
)
)
)
(cell FDP (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port D (direction INPUT))
(port C (direction INPUT))
(port PRE (direction INPUT))
(port Q (direction OUTPUT))
)
)
)
(cell FDPE (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port D (direction INPUT))
(port C (direction INPUT))
(port CE (direction INPUT))
(port PRE (direction INPUT))
(port Q (direction OUTPUT))
)
)
)
(cell FDR (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port D (direction INPUT))
(port C (direction INPUT))
(port R (direction INPUT))
(port Q (direction OUTPUT))
)
)
)
(cell FDRE (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port D (direction INPUT))
(port C (direction INPUT))
(port CE (direction INPUT))
(port R (direction INPUT))
(port Q (direction OUTPUT))
)
)
)
(cell FDRS (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port D (direction INPUT))
(port C (direction INPUT))
(port R (direction INPUT))
(port S (direction INPUT))
(port Q (direction OUTPUT))
)
)
)
(cell FDS (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port D (direction INPUT))
(port C (direction INPUT))
(port S (direction INPUT))
(port Q (direction OUTPUT))
)
)
)
(cell INV (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port I (direction INPUT))
(port O (direction OUTPUT))
)
)
)
(cell LUT1 (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port I0 (direction INPUT))
(port O (direction OUTPUT))
)
)
)
(cell LUT2 (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port I0 (direction INPUT))
(port I1 (direction INPUT))
(port O (direction OUTPUT))
)
)
)
(cell LUT3 (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port I0 (direction INPUT))
(port I1 (direction INPUT))
(port I2 (direction INPUT))
(port O (direction OUTPUT))
)
)
)
(cell LUT4 (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port I0 (direction INPUT))
(port I1 (direction INPUT))
(port I2 (direction INPUT))
(port I3 (direction INPUT))
(port O (direction OUTPUT))
)
)
)
(cell MUXCY (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port DI (direction INPUT))
(port CI (direction INPUT))
(port S (direction INPUT))
(port O (direction OUTPUT))
)
)
)
(cell MUXCY_L (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port DI (direction INPUT))
(port CI (direction INPUT))
(port S (direction INPUT))
(port LO (direction OUTPUT))
)
)
)
(cell MUXF5 (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port I0 (direction INPUT))
(port I1 (direction INPUT))
(port S (direction INPUT))
(port O (direction OUTPUT))
)
)
)
(cell MUXF6 (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port I0 (direction INPUT))
(port I1 (direction INPUT))
(port S (direction INPUT))
(port O (direction OUTPUT))
)
)
)
(cell RAMB4_S1_S16 (cellType GENERIC)
(view view_1 (viewType NETLIST)
(interface
(port WEA (direction INPUT))
(port ENA (direction INPUT))
(port RSTA (direction INPUT))
(port CLKA (direction INPUT))
(port (rename DIA_0_ "DIA<0>") (direction INPUT))
(port (rename DOA_0_ "DOA<0>") (direction OUTPUT))
(port (rename ADDRA_0_ "ADDRA<0>") (direction INPUT))
(port (rename ADDRA_1_ "ADDRA<1>") (direction INPUT))
(port (rename ADDRA_2_ "ADDRA<2>") (direction INPUT))
(port (rename ADDRA_3_ "ADDRA<3>") (direction INPUT))
(port (rename ADDRA_4_ "ADDRA<4>") (direction INPUT))
(port (rename ADDRA_5_ "ADDRA<5>") (direction INPUT))
(port (rename ADDRA_6_ "ADDRA<6>") (direction INPUT))
(port (rename ADDRA_7_ "ADDRA<7>") (direction INPUT))
(port (rename ADDRA_8_ "ADDRA<8>") (direction INPUT))
(port (rename ADDRA_9_ "ADDRA<9>") (direction INPUT))
(port (rename ADDRA_10_ "ADDRA<10>") (direction INPUT))
(port (rename ADDRA_11_ "ADDRA<11>") (direction INPUT))
(port WEB (direction INPUT))
(port ENB (direction INPUT))
(port RSTB (direction INPUT))
(port CLKB (direction INPUT))
(port (rename DIB_0_ "DIB<0>") (direction INPUT))
(port (rename DIB_1_ "DIB<1>") (direction INPUT))
(port (rename DIB_2_ "DIB<2>") (direction INPUT))
(port (rename DIB_3_ "DIB<3>") (direction INPUT))
(port (rename DIB_4_ "DIB<4>") (direction INPUT))
(port (rename DIB_5_ "DIB<5>") (direction INPUT))
(port (rename DIB_6_ "DIB<6>") (direction INPUT))
(port (rename DIB_7_ "DIB<7>") (direction INPUT))
(port (rename DIB_8_ "DIB<8>") (direction INPUT))
(port (rename DIB_9_ "DIB<9>") (direction INPUT))
(port (rename DIB_10_ "DIB<10>") (direction INPUT))
(port (rename DIB_11_ "DIB<11>") (direction INPUT))
(port (rename DIB_12_ "DIB<12>") (direction INPUT))
(port (rename DIB_13_ "DIB<13>") (direction INPUT))
(port (rename DIB_14_ "DIB<14>") (direction INPUT))
(port (rename DIB_15_ "DIB<15>") (direction INPUT))
(port (rename DOB_0_ "DOB<0>") (direction OUTPUT))
(port (rename DOB_1_ "DOB<1>") (direction OUTPUT))
(port (rename DOB_2_ "DOB<2>") (direction OUTPUT))
(port (rename DOB_3_ "DOB<3>") (direction OUTPUT))
(port (rename DOB_4_ "DOB<4>") (direction OUTPUT))
(port (rename DOB_5_ "DOB<5>") (direction OUTPUT))
(port (rename DOB_6_ "DOB<6>") (direction OUTPUT))
(port (rename DOB_7_ "DOB<7>") (direction OUTPUT))
(port (rename DOB_8_ "DOB<8>") (direction OUTPUT))
(port (rename DOB_9_ "DOB<9>") (direction OUTPUT))
(port (rename DOB_10_ "DOB<10>") (direction OUTPUT))
(port (rename DOB_11_ "DOB<11>") (direction OUTPUT))
(port (rename DOB_12_ "DOB<12>") (direction OUTPUT))
(port (rename DOB_13_ "DOB<13>") (direction OUTPUT))
(port (rename DOB_14_ "DOB<14>") (direction OUTPUT))
(port (rename DOB_15_ "DOB<15>") (direction OUTPUT))
(port (rename ADDRB_0_ "ADDRB<0>") (direction INPUT))
(port (rename ADDRB_1_ "ADDRB<1>") (direction INPUT))
(port (rename ADDRB_2_ "ADDRB<2>") (direction INPUT))
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