Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 1.FlipFlop state_FFd1 has been replicated 1 time(s)FlipFlop state_FFd4 has been replicated 1 time(s)=========================================================================*                            Final Report                               *=========================================================================Final ResultsRTL Top Level Output File Name     : top.ngrTop Level Output File Name         : topOutput Format                      : NGCOptimization Goal                  : SpeedKeep Hierarchy                     : NODesign Statistics# IOs                              : 45Macro Statistics :# Registers                        : 8#      1-bit register              : 3#      11-bit register             : 1#      16-bit register             : 2#      8-bit register              : 2# Tristates                        : 1#      8-bit tristate buffer       : 1# Adders/Subtractors               : 2#      11-bit adder                : 1#      16-bit adder                : 1Cell Usage :# BELS                             : 155#      GND                         : 1#      LUT1                        : 12#      LUT1_D                      : 1#      LUT1_L                      : 16#      LUT2                        : 11#      LUT2_L                      : 1#      LUT3                        : 1#      LUT3_D                      : 4#      LUT3_L                      : 1#      LUT4                        : 6#      LUT4_L                      : 50#      MUXCY                       : 25#      VCC                         : 1#      XORCY                       : 25# FlipFlops/Latches                : 68#      FD                          : 11#      FDE                         : 32#      FDRE                        : 21#      FDSE                        : 4# Clock Buffers                    : 1#      BUFGP                       : 1# IO Buffers                       : 44#      IBUF                        : 2#      IOBUF                       : 8#      OBUF                        : 34=========================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-4  Number of Slices:                      58  out of   3584     1%   Number of Slice Flip Flops:            68  out of   7168     0%   Number of 4 input LUTs:               103  out of   7168     1%   Number of bonded IOBs:                 44  out of    141    31%   Number of GCLKs:                        1  out of      8    12%  =========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT      GENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+clk                                | BUFGP                  | 11    |count_10:Q                         | NONE                   | 57    |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -4   Minimum period: 2.138ns (Maximum Frequency: 467.727MHz)   Minimum input arrival time before clock: 3.208ns   Maximum output required time after clock: 6.045ns   Maximum combinational path delay: No path foundTiming Detail:--------------All values displayed in nanoseconds (ns)-------------------------------------------------------------------------Timing constraint: Default period analysis for Clock 'clk'Delay:               1.347ns (Levels of Logic = 2)  Source:            count_10 (FF)  Destination:       count_10 (FF)  Source Clock:      clk rising  Destination Clock: clk rising  Data Path: count_10 to count_10                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FD:C->Q              58   0.000   1.347  count_10 (count_10)     LUT1:I0->O            0   0.000   0.000  count<10>_rt (count<10>_rt)     XORCY:LI->O           1   0.000   0.000  count_Madd__n0000_inst_sum_26 (count__n0000<10>)     FD:D                      0.000          count_10    ----------------------------------------    Total                      1.347ns (0.000ns logic, 1.347ns route)                                       (0.0% logic, 100.0% route)-------------------------------------------------------------------------Timing constraint: Default period analysis for Clock 'count_10:Q'Delay:               2.138ns (Levels of Logic = 1)  Source:            is_end (FF)  Destination:       data_out_7 (FF)  Source Clock:      count_10:Q rising  Destination Clock: count_10:Q rising  Data Path: is_end to data_out_7                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FDRE:C->Q            13   0.000   0.895  is_end (is_end)     LUT2:I1->O           23   0.000   1.243  fifodata_N1701_9 (fifodata_N1701_9)     FDE:CE                    0.000          fifodata_7    ----------------------------------------    Total                      2.138ns (0.000ns logic, 2.138ns route)                                       (0.0% logic, 100.0% route)-------------------------------------------------------------------------Timing constraint: Default OFFSET IN BEFORE for Clock 'count_10:Q'Offset:              3.208ns (Levels of Logic = 2)  Source:            reset (PAD)  Destination:       data_out_7 (FF)  Destination Clock: count_10:Q rising  Data Path: reset to data_out_7                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     IBUF:I->O            35   0.641   1.324  reset_IBUF (reset_IBUF)     LUT2:I0->O           23   0.000   1.243  fifodata_N1701_9 (fifodata_N1701_9)     FDE:CE                    0.000          fifodata_7    ----------------------------------------    Total                      3.208ns (0.641ns logic, 2.567ns route)                                       (20.0% logic, 80.0% route)-------------------------------------------------------------------------Timing constraint: Default OFFSET OUT AFTER for Clock 'count_10:Q'Offset:              6.045ns (Levels of Logic = 1)  Source:            slwr (FF)  Destination:       slwr (PAD)  Source Clock:      count_10:Q rising  Data Path: slwr to slwr                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FDSE:C->Q             2   0.000   0.465  slwr (slwr_OBUF)     OBUF:I->O                 5.580          slwr_OBUF (slwr)    ----------------------------------------    Total                      6.045ns (5.580ns logic, 0.465ns route)                                       (92.3% logic, 7.7% route)=========================================================================CPU : 6.48 / 8.69 s | Elapsed : 7.00 / 9.00 s --> Total memory usage is 71228 kilobytes