library	ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.mydefine.all;

entity control is
	port(c_en:in std_logic;
	input:in std_logic_vector(7 downto 0);
	clk:in std_logic;
	output:out unsigned(18 downto 0));
end control;

architecture str of control is
signal address:std_logic_vector(rank-1 downto 0);
signal coef:std_logic_vector(10 downto 0);
signal sam_en:std_logic;
signal r:std_logic;

component filter is
     port(indata:in std_logic_vector(7 downto 0);
     outdata:out std_logic_vector(rank-1 downto 0);
     add_en:out std_logic;  
     en:in std_logic;
     clk:in std_logic;
     rf:in std_logic);
end component;

component lut is
     port (addr:in std_logic_vector(rank-1 downto 0);
	outdata:out std_logic_vector(10 downto 0);
	clk:in std_logic);
end component;

component shift_add is
 	port(indata:in std_logic_vector(10 downto 0);
    clk:in std_logic;
    add_en: in std_logic;
    outdata:out unsigned(18 downto 0);
    rs:out std_logic);
end component;

begin
	c1:filter
	port map(en=>c_en,indata=>input,clk=>clk,outdata=>address,add_en=>sam_en,rf=>r);

	c2:lut
	port map(addr=>address,clk=>clk,outdata=>coef);

	c3:shift_add
	port map(indata=>coef,clk=>clk,outdata=>output,add_en=>sam_en,rs=>r);
end str;