MODELDATA
MODELDATA_VERSION "v1998.8"
DESIGN "regd1";

/* port drive, load, max capacitance and max transition in data file */
PORTDATA
rd: MAXTRANS(0.0);
cs: MAXTRANS(0.0);
din: MAXTRANS(0.0);
dout: MAXTRANS(0.0);
ENDPORTDATA

/* timing arc data */
TIMINGDATA

ARCDATA
rd_dout_delay:
CELL_RISE(scalar) {
  VALUES("4.5");
}
CELL_FALL(scalar) {
  VALUES("4.5");
}
ENDARCDATA

ARCDATA
cs_rd_setup:
CONSTRAINT(scalar) {
  VALUES("6");
}
ENDARCDATA

ARCDATA
din_rd_setup:
CONSTRAINT(scalar) {
  VALUES("6");
}
ENDARCDATA

ARCDATA
cs_rd_hold:
CONSTRAINT(scalar) {
  VALUES("-1.5");
}
ENDARCDATA

ARCDATA
din_rd_hold:
CONSTRAINT(scalar) {
  VALUES("-1.5");
}
ENDARCDATA

ENDTIMINGDATA
ENDMODELDATA