library IEEE;
use IEEE.std_logic_1164.all;
use WORK.UART_PACKAGE.all;

entity uart_top is

  generic(
     -- 數據位個數
	DATA_BIT : integer := 8;
	-- 總數據個數
	TOTAL_BIT : integer := 10;
	-- 奇偶校驗規則
	PARITY_RULE : PARITY := NONE;
	--完整波特率時鐘對應的計數
	FULL_PULSE_COUNT : BD_COUNT := BD9600_FPC;
	--波特率時鐘上升沿對應的計數
	RISE_PULSE_COUNT : BD_COUNT := BD9600_HPC 
  );
  port(
	  -- 時鐘信號
       clk : in STD_LOGIC;
	  -- 復位信號
       reset_n : in STD_LOGIC;
	  -- 發送控制信號
       send : in STD_LOGIC;
	  -- 數據發送總線
       send_bus : in STD_LOGIC_VECTOR(DATA_BIT-1 downto 0);
	  -- 發送完成信號
       send_over : out STD_LOGIC;
	  -- 錯誤提示信號
       error : out STD_LOGIC;
	  -- 接收提示信號
       recv : out STD_LOGIC;
	  -- 數據接收總線
       recv_bus : out STD_LOGIC_VECTOR(DATA_BIT-1 downto 0);
	  -- RS-232數據接收端口
       RxD : in STD_LOGIC;
	  -- RS-232數據發送端口
       TxD : out STD_LOGIC );
end uart_top;

architecture uart_top of uart_top is

-- 波特率發生器組件聲明
component baudrate_generator
  generic(
       FULL_PULSE_COUNT : BD_COUNT := BD9600_FPC;
       RISE_PULSE_COUNT : BD_COUNT := BD9600_HPC
  );
  port (
       ce : in STD_LOGIC;
       clk : in STD_LOGIC;
       reset_n : in STD_LOGIC;
       bg_out : out STD_LOGIC;
       indicator : out STD_LOGIC
  );
end component;
-- 計數器組件聲明
component counter
  generic(
       MAX_COUNT : INTEGER := 10
  );
  port (
       ce : in STD_LOGIC;
       clk : in STD_LOGIC;
       reset_n : in STD_LOGIC;
       overflow : out STD_LOGIC
  );
end component;
-- 信號監測器
component detector
  port (
       RxD : in STD_LOGIC;
       clk : in STD_LOGIC;
       reset_n : in STD_LOGIC;
       new_data : out STD_LOGIC
  );
end component;
-- 奇偶校驗器
component parity_verifier
  generic(
       DATA_LENGTH : INTEGER := DATA_BIT;
       PARITY_RULE : PARITY := PARITY_RULE
  );
  port (
       source : in STD_LOGIC_VECTOR(DATA_LENGTH-1 downto 0);
       parity : out STD_LOGIC
  );
end component;
-- 移位寄存器
component shift_register
  generic(
       TOTAL_BIT : INTEGER := TOTAL_BIT
  );
  port (
       clk : in STD_LOGIC;
       din : in STD_LOGIC;
       reset_n : in STD_LOGIC;
       dout : out STD_LOGIC;
       regs : out STD_LOGIC_VECTOR(TOTAL_BIT-1 downto 0)
  );
end component;
-- 二選一選擇器
component switch
  port (
       din1 : in STD_LOGIC;
       din2 : in STD_LOGIC;
       sel : in STD_LOGIC;
       dout : out STD_LOGIC
  );
end component;
-- 總線選擇器
component switch_bus
  generic(
       BUS_WIDTH : INTEGER := DATA_BIT
  );
  port (
       din1 : in STD_LOGIC_VECTOR(BUS_WIDTH-1 downto 0);
       din2 : in STD_LOGIC_VECTOR(BUS_WIDTH-1 downto 0);
       sel : in STD_LOGIC;
       dout : out STD_LOGIC_VECTOR(BUS_WIDTH-1 downto 0)
  );
end component;
-- UART內核
component uart_core
  generic(
       DATA_BIT : INTEGER := DATA_BIT;
       PARITY_RULE : PARITY := PARITY_RULE;
       TOTAL_BIT : INTEGER := TOTAL_BIT
  );
  port (
       clk : in STD_LOGIC;
       new_data : in STD_LOGIC;
       overflow : in STD_LOGIC;
       parity : in STD_LOGIC;
       regs : in STD_LOGIC_VECTOR(TOTAL_BIT-1 downto 0);
       reset_n : in STD_LOGIC;
       send : in STD_LOGIC;
       send_bus : in STD_LOGIC_VECTOR(DATA_BIT-1 downto 0);
       ce_parts : out STD_LOGIC;
       error : out STD_LOGIC;
       recv : out STD_LOGIC;
       recv_bus : out STD_LOGIC_VECTOR(DATA_BIT-1 downto 0);
       reset_dt : out STD_LOGIC;
       reset_parts : out STD_LOGIC;
       sel_clk : out STD_LOGIC;
       sel_out : out STD_LOGIC;
       sel_pv : out STD_LOGIC;
       sel_si : out STD_LOGIC;
       send_over : out STD_LOGIC;
       send_si : out STD_LOGIC
  );
end component;

----     常數     -----
constant VCC_CONSTANT   : STD_LOGIC := '1';
---- 內部信號聲明 ----
signal bg_clk : STD_LOGIC;
signal bg_out : STD_LOGIC;
signal ce_parts : STD_LOGIC;
signal clk_inv : STD_LOGIC;
signal counter_clk : STD_LOGIC;
signal indicator : STD_LOGIC;
signal new_data : STD_LOGIC;
signal overflow : STD_LOGIC;
signal parity : STD_LOGIC;
signal reset_dt : STD_LOGIC;
signal reset_parts : STD_LOGIC;
signal sel_clk : STD_LOGIC;
signal sel_out : STD_LOGIC;
signal sel_pv : STD_LOGIC;
signal sel_si : STD_LOGIC;
signal send_si : STD_LOGIC;
signal sr_in : STD_LOGIC;
signal sr_out : STD_LOGIC;
signal VCC : STD_LOGIC;
signal pv_source : STD_LOGIC_VECTOR (DATA_BIT-1 downto 0);
signal recv_parity_source : STD_LOGIC_VECTOR (DATA_BIT-1 downto 0);
signal regs : STD_LOGIC_VECTOR (TOTAL_BIT-1 downto 0);
signal send_parity_source : STD_LOGIC_VECTOR (DATA_BIT-1 downto 0);

begin

	-- 信號連接
	clk_inv <= not clk;	 
	VCC <= VCC_CONSTANT;   
	send_parity_source <= send_bus;
	recv_bus <= recv_parity_source;

	-- 波特率發生器實例
	U_BG : baudrate_generator
	  port map(
	       bg_out => bg_out,
	       ce => ce_parts,
	       clk => clk,
	       indicator => indicator,
	       reset_n => reset_parts
	  );
	-- 總線選擇器實例
	U_BusSwitch : switch_bus
	  port map(
	       din1 => send_parity_source( DATA_BIT-1 downto 0 ),
	       din2 => recv_parity_source( DATA_BIT-1 downto 0 ),
	       dout => pv_source( DATA_BIT-1 downto 0 ),
	       sel => sel_pv
	  );
	-- UART內核實例
	U_Core : uart_core
	  port map(
	       ce_parts => ce_parts,
	       clk => clk,
	       error => error,
	       new_data => new_data,
	       overflow => overflow,
	       parity => parity,
	       recv => recv,
	       recv_bus => recv_parity_source( DATA_BIT-1 downto 0 ),
	       regs => regs( TOTAL_BIT-1 downto 0 ),
	       reset_dt => reset_dt,
	       reset_n => reset_n,
	       reset_parts => reset_parts,
	       sel_clk => sel_clk,
	       sel_out => sel_out,
	       sel_pv => sel_pv,
	       sel_si => sel_si,
	       send => send,
	       send_bus => send_parity_source( DATA_BIT-1 downto 0 ),
	       send_over => send_over,
	       send_si => send_si
	  );
	-- 計數器實例
	U_Counter : counter
	  port map(
	       ce => ce_parts,
	       clk => counter_clk,
	       overflow => overflow,
	       reset_n => reset_parts
	  );
	-- 計數器時鐘源選擇器
	U_CounterClkSwitch : switch
	  port map(
	       din1 => indicator,
	       din2 => clk_inv,
	       dout => counter_clk,
	       sel => sel_clk
	  );
	-- 信號監測器
	U_Detector : detector
	  port map(
	       RxD => RxD,
	       clk => clk,
	       new_data => new_data,
	       reset_n => reset_dt
	  );
	-- 奇偶校驗器
	U_ParityVerifier : parity_verifier
	  port map(
	       parity => parity,
	       source => pv_source( DATA_BIT-1 downto 0 )
	  );
	-- 移位寄存器輸入源選擇器實例
	U_SISwitch : switch
	  port map(
	       din1 => send_si,
	       din2 => RxD,
	       dout => sr_in,
	       sel => sel_si
	  );
	-- 移位寄存器實例
	U_SR : shift_register
	  port map(
	       clk => bg_clk,
	       din => sr_in,
	       dout => sr_out,
	       regs => regs( TOTAL_BIT-1 downto 0 ),
	       reset_n => reset_parts
	  );
	-- 移位寄存器時鐘源選擇器實例
	U_SRClkSwitch : switch
	  port map(
	       din1 => bg_out,
	       din2 => clk_inv,
	       dout => bg_clk,
	       sel => sel_clk
	  );
	-- 輸出選擇器實例
	U_TXDSwitch : switch
	  port map(
	       din1 => VCC,
	       din2 => sr_out,
	       dout => TxD,
	       sel => sel_out
	  );

end uart_top;