-- INVS modelUSE WORK.ALL;entity INV is     generic(constant TPLH:TIME:=2 ns;            constant TPHL:TIME:=3 ns);    port (I1:in BIT; O: out BIT);end INV;architecture BEH of INV isbegin P1: process(I1)begin   if (I1='1') then      O<= not I1 after TPHL;      else O<=not I1 after TPLH;   end if;  end process P1;       end BEH;   --COMPUSE WORK.ALL;entity COMP isport(SR: in BIT_VECTOR(3 downto 0);     reg_out: in BIT_VECTOR(3 downto 0);     xnor_out: out BIT_VECTOR(3 downto 0));end COMP;architecture BEH of COMP is   component XOR2C   port(I1,I2:in BIT; O: out BIT);   end component;      component INVC   port(I1:in BIT; O: out BIT);   end component;       for all : xor2c use entity xor2(BEH);   for all : INVC use entity INV(BEH);   signal A0,A1,A2,A3,A4,A5,A6,A7:BIT;  beginG0:XOR2C	port map( sr(0),reg_out(0), A0);G1:XOR2C	port map( sr(1),reg_out(1), A1);		G2:XOR2C	port map( sr(2),reg_out(2), A2);G3:XOR2C	port map( sr(3),reg_out(3), A3);		G4:INVC	port map(A0, A4);G5:INVC	port map(A1,A5);		G6:INVC	port map(A2,A6);G7:INVC	port map(A3,A7);				xnor_OUT(0)<=A4;XNOR_OUT(1)<=A5;	XNOR_OUT(2)<=A6;XNOR_OUT(3)<=A7;end BEH;