-- DFF modelUSE WORK.ALL;-- OR2 MODELUSE WORK.ALL;entity OR2 is    generic(constant TPLH:TIME:=4 ns;            constant TPHL:TIME:=6 ns);	    port ( I1,I2:in BIT; O: out BIT);end OR2;architecture BEH of OR2 ISbeginP1: process(I1)variable O_TEM:BIT:='0';variable O_TEM_M:BIT; 	BEGIN	O_TEM_M := I1 OR I2 ;	if ( O_TEM='0' AND O_TEM_M='1') then	   O <= I1 OR I2 after TPLH;	   elsif (O_TEM='1' AND O_TEM_M='0') then	        O <= I1 OR I2 after TPHL; 	        else O <= I1 OR I2 ;	 end if;	  O_TEM:= I1 OR I2 ;end process P1;end BEH;--AND2 MODELUSE WORK.ALL;entity AND2 is    generic(constant TPLH:TIME:=4 ns;            constant TPHL:TIME:=6 ns);	    port ( I1,I2:in BIT; O: out BIT);end AND2;architecture BEH of AND2 ISbeginP1: process(I1)variable O_TEM:BIT:='0';variable O_TEM_M:BIT; 	BEGIN	O_TEM_M := I1 AND I2 ;	if ( O_TEM='0' AND O_TEM_M='1') then	   O <= I1 AND I2 after TPLH;	   elsif (O_TEM='1' AND O_TEM_M='0') then	        O <= I1 AND I2 after TPHL; 	        else O <= I1 AND I2 ;	 end if;	  O_TEM:= I1 AND I2 ;end process P1;end BEH;--XOR2 MODELUSE work.ALL;entity XOR2 is    generic(constant TPLH:TIME:=4 ns;            constant TPHL:TIME:=6 ns);	    port ( I1,I2: in BIT; O: out BIT);end XOR2;architecture BEH of XOR2 isbeginP1: process(I1)variable O_TEM:BIT;variable O_TEM_M:BIT; 	BEGIN	O_TEM_M := I1 XOR I2;	if ( O_TEM='0' AND O_TEM_M='1') then	   O <= I1 XOR I2 after TPLH;	   elsif (O_TEM='1' AND O_TEM_M='0') then	        O <= I1 XOR I2 after TPHL; 	        else O <= I1 XOR I2;	 end if;	 O_TEM:= I2 XOR I2;end process P1;end BEH;---shifterUSE WORK.ALL;entity SHIFTER_a isport (B: in BIT_VECTOR(3 DOWNTO 0);      load: in BIT;      shift: in BIT;      clk:in BIT;      reset:in BIT;       sr: out BIT_VECTOR(3 downto 0));end shifter_a;architecture BEH of SHIFTER_a is   component and2c   port(I1,I2:in BIT; O: out BIT);   end component;      component XOR2c   port(I1,I2:in BIT; O: out BIT);   end component;      component or2c   port(I1,I2:in BIT; O: out BIT);   end component;      component dffc   port (D, clk ,reset : in BIT;  	 Q : out BIT);   end component;            for all : dffc use entity DFF(BEH);   for all : OR2C use entity OR2(BEH);   for all : AND2C use entity AND2(BEH);   for all : XOR2C use entity XOR2(BEH);   signal A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,A13,A14,A15,A16: BIT;      begin--FIRST INPUTG0: AND2C        port map (shift, A13, A0);G1: AND2C        port map (B(0), load, A1);        G2: AND2C        port map (shift, A14, A2);                G3: AND2C        port map (B(1), load, A3);               -- THIRD INPUT       G4: AND2C        port map (shift, A15, A4);G5: AND2C        port map (B(2), load, A5);        G6: AND2C        port map (shift, A16, A6);                G7: AND2C        port map (B(3), load, A7);               --SECOND LEVEL        G8: OR2C 	PORT MAP (A0,A1,A8);	G9: OR2C 	PORT MAP (A2,A3,A9);		             G10: OR2C 	PORT MAP (A4,A5,A10);	G11: OR2C 	PORT MAP (A6,A7,A11);	   --THIRD LEVELG12: DFFC	port map (A8, clk ,reset, A12);           G13: DFFC	port map (A9, clk ,reset, A13);                          G14: DFFC	port map (A10, clk ,reset, A14);                        G15: DFFC	port map (A11, clk ,reset, A15);  	G16: XOR2C	port map ( A12,A13, A16);--sr(0)<=A12;--sr(1)<=A13;--sr(2)<=A14;--SR(3)<=A15;sr<=b;END BEH;