entity TEST_BENCH isend TEST_BENCH;use work.all;architecture AUTOCOR1 of TEST_BENCH is    SIGNAL B: BIT_VECTOR(3 downto 0);    SIGNAL A: BIT_VECTOR(2 downto 0);    SIGNAL RUN:BIT;    SIGNAL RST:BIT;    SIGNAL LOAD:BIT;    SIGNAL CLK:BIT;    SIGNAL SHIFT:BIT;          component OSCILLATOR      generic (HI_TIME,LO_TIME:TIME);      port (RUN: in BIT; CLK: out BIT :='0');      end component;          component AUTOCORGEN          --generic (RDEL,CLKDEL:TIME);         port(B: in BIT_VECTOR(3 downto 0);         LOAD : in BIT;         SHIFT: IN BIT;         CLK: in BIT;         RST: in BIT;         Acout: out BIT_VECTOR(2 downto 0));      end component;               for L1: OSCILLATOR use entity  COSC(ALG);     for L2: AUTOCORGEN use entity  auto(behaver);           begin     L1: OSCILLATOR     generic map(100 ns, 100 ns)     port map(RUN,CLK);          L2: AUTOCORGEN     --generic map(13 ns,10 ns)     port map(B,CLK,A);                               RST <= '0',       	      '1' after 3200 ns;       	     -- '1' after 6400 ns,           	     -- '1' after 9600 ns,       	     -- '1' after 12800 ns,         	     -- '1' after 16000 ns;       	             	             RUN <= '1','0' after 3100 ns;          B <= "0111" ;                   --   "0001" after 3200 ns,            --   "0010" after 6400 ns,            -- "0011" after 9600 ns,            --  "0100" after 12800 ns,            --   "0101" after 16000 ns;                                   LOAD <=  '1','0'after 50 ns;       		--'1' after 3200 ns,'0' after 3250 ns,        		--'1' after 6400 ns,'0' after 6450 ns,       		--'1' after 9600 ns,'0' after 9650 ns,       		--'1' after 12800 ns,'0' after 12850 ns,        		--'1' after 16000 ns,'0' after 16050 ns;       		        SHIFT <='0', '1' after 50 ns,        		'0' after 3190 ns;        	--'1'  after 3210 ns,'0' after 6350 ns,        	--'1'  after 6410 ns,'0' after 9550 ns,        	--'1'  after 9610 ns,'0' after 12750 ns,        	--'1'  after 12810 ns,'0' after 15950 ns;      		            end AUTOCOR1;