entity TEST_BENCH isend TEST_BENCH;use work.all;architecture AUTOCOR1 of TEST_BENCH is    signal B: BIT_VECTOR(3 downto 0);    signal A: BIT_VECTOR(2 downto 0);    SIGNAL RUN:BIT;    SIGNAL RST:BIT;    SIGNAL LOAD:BIT;    SIGNAL CLOCK:BIT;          component OSCILLATOR      generic (HI_TIME,LO_TIME:TIME);      port (RUN: in BIT; CLOCK: out BIT :='0');      end component;          component AUTOCORGEN          --generic (RDEL,CLKDEL:TIME);         port(B: in BIT_VECTOR(3 downto 0);         CLOCK: in BIT;         RST: in BIT;         LOAD : in BIT;         A: out BIT_VECTOR(2 downto 0));      end component;         for L1:   OSCILLATOR use entity  COSC(ALG);     for L2: AUTOCORGEN use entity  AUTOCOR(BEH);               begin     L1: OSCILLATOR     generic map(100 ns, 100 ns)     port map(RUN,CLOCK);          L2: AUTOCORGEN     --generic map(13 ns,10 ns)     port map(B,CLOCK,RST,LOAD,A);                       RST <= '0', '1' after 3200 ns;            RUN <= '1','0' after 10000 ns;          B <= "0110" ,                        "0101" after 3200 ns,               "0110" after 6400 ns,               "0111" after 9600 ns;                    LOAD <= '1','0'after 50 ns,'1' after 3200 ns,'0'after 3250 ns, '1' after 6400 ns,'0' after 6450 ns,'1' after 9600 ns,'0' after 9650 ns;                        end AUTOCOR1;