Revised: 1/31/00 MPGDesign Description: PN Generator Using the Virtex SRL MacroFor a full functional description see Application Note 211.Design Type: ISE (chip V300 BG432 -6)Source File: pn_gen_srl_test.tf   - Top-level, self-checking test bench that instantiates the pn generator. This verilog test bench works with both (Verilog and VHDL) versions of the design. ModelSim EE Plus/5.2e will support mixed HDL simulations.iq_pn_gen.v          - Verilog RTL version of pn generator code.pni_gold.dat         - "Golden" I channel data used by the test bench to compare against actual                       pn sequence generated by the design.pnq_gold.dat         - "Golden" Q channel data used by the test bench to compare against actual                       pn sequence generated by the design.Synthesis:Comments are provided in the verilog (iq_pn_gen.v) PN generator RTL code that indicate what parameters are available to customize the implementation.  The number of taps are fixed however the tap points and LFSR width are parameratizable.  All three synthesis vendors, Synplify 2.2.2a, FPGA Express 3.3, and Leonardo v1999.1g were used to implement the LFSRs very efficiently utilizing the Virtex Shift Register LUT (SRL16E).  The code provides a `define compiler directive that can be used to steer the code to infer Flip-flops instead of SRL16E elements.  This can be useful allowing the code to be written such that it takes advantage of the Virtex SRL16Es when targetting Virtex, but also allows for easy portability to other non-Virtex technologies.Simulation:Requires the following simulation libraries:	Unisims	SimprimsUsing ModelSim, compile the pn_gen_srl_test.v and either the verilog version (iq_pn_gen.v)or VHDL version (iq_pn_gen.vhd) of the pn generator.  The clock period is set in the test bench for 10ns.  The example LFSRs in the code have a length of 17 bits wide therefore theywill produce a pn sequence 2^^17 - 1 bits long (before repeating).  Run the simulation for approximately 1.32 ms to simulate the entire sequence.  (At a 10 ns clock period, the entiresequence will take 1,310,710 ns.)The test bench is self-checking and will compare the output of the I channel LFSR and Q channelLFSR with "golden" data from the pni_gold.dat and pnq_gold.dat files, respectively.  Each bit comparison is reported in the command window showing the simulation time, the golden bit value, and the actual bit value.  If there's a mismatch between the two bits, the simluation will stop.  The test bench will also produce two files containing the actual bits generated.  Bits generatedfrom the I channel LFSR will be written in a file called pni_testout.dat, and bits generatedfrom the Q channel LFSR will be written in a file called pnq_testout.dat.NOTE:  This design has been tested and is known to compile and implementcorrectly using XST Synthesis flow.Other synthesis flows are unsupported and may encounter errors in eithersynthesis or implementation.NOTE: If you are trying to run this example in a read-only location,    the design hierachy will not display properly. Please copy the example  project to a new location by using either Project Save As... from the File menupulldown in ISE or some other method of your choice. Copy the example to a locationwhere you have write permissions and the hiearchy will display properly.