?? test.hier_info
字號:
|TEST
MOSI <= SPI:inst.MOSI
GCLK => SPI:inst.CLK
GCLK => counter25:inst5.clock
WR => SPI:inst.WR
RD => SPI:inst.RD
RD => INTERFACE:inst1.RD
MIMO => SPI:inst.MISO
MIMO => T_MISO.DATAIN
RESET2 => SPI:inst.RESET
RESET2 => RESETTEST.DATAIN
RESET2 => inst7.IN0
RFirq => SPI:inst.RFirq
RFirq => T_IRQ.DATAIN
RFirq => inst4.DATAIN
ADDR[0] => SPI:inst.ADDR[0]
ADDR[1] => SPI:inst.ADDR[1]
ADDR[2] => SPI:inst.ADDR[2]
ADDR[3] => SPI:inst.ADDR[3]
ADDR[4] => SPI:inst.ADDR[4]
ADDR[5] => SPI:inst.ADDR[5]
ADDR[6] => SPI:inst.ADDR[6]
ADDR[7] => SPI:inst.ADDR[7]
ADDR[8] => SPI:inst.ADDR[8]
ADDR[9] => SPI:inst.ADDR[9]
ADDR[10] => SPI:inst.ADDR[10]
ADDR[11] => SPI:inst.ADDR[11]
ECS[1] => INTERFACE:inst1.ECS[1]
ECS[2] => INTERFACE:inst1.ECS[2]
ECS[2] => inst3.IN0
ECS[2] => SPI:inst.ECS[2]
XDATA[0] <= INTERFACE:inst1.XDATA[0]
XDATA[1] <= INTERFACE:inst1.XDATA[1]
XDATA[2] <= INTERFACE:inst1.XDATA[2]
XDATA[3] <= INTERFACE:inst1.XDATA[3]
XDATA[4] <= INTERFACE:inst1.XDATA[4]
XDATA[5] <= INTERFACE:inst1.XDATA[5]
XDATA[6] <= INTERFACE:inst1.XDATA[6]
XDATA[7] <= INTERFACE:inst1.XDATA[7]
IRQ <= SPI:inst.IRQ
CSN <= SPI:inst.CSN
SCK <= SPI:inst.SCK
CE <= SPI:inst.CE
TEST <= SPI:inst.SFTEst
TEST8 <= SPI:inst.SFTEst1
RESETTEST <= RESET2.DB_MAX_OUTPUT_PORT_TYPE
T_MOSI <= SPI:inst.MOSI
T_IRQ <= RFirq.DB_MAX_OUTPUT_PORT_TYPE
T_SCK <= SPI:inst.SCK
T_CE <= SPI:inst.CE
T_CSN <= SPI:inst.CSN
T_MISO <= MIMO.DB_MAX_OUTPUT_PORT_TYPE
RFINT <= inst4.PADIO
EINT2 <= Q[15].DB_MAX_OUTPUT_PORT_TYPE
LEDDATA[0] <= Q[21].DB_MAX_OUTPUT_PORT_TYPE
LEDDATA[1] <= Q[22].DB_MAX_OUTPUT_PORT_TYPE
LEDDATA[2] <= Q[23].DB_MAX_OUTPUT_PORT_TYPE
LEDDATA[3] <= Q[24].DB_MAX_OUTPUT_PORT_TYPE
RESET1 => ~NO_FANOUT~
|TEST|SPI:inst
MOSI <= spiprocess:inst21.mosi
CLK => spiprocess:inst21.clk
RD => spiprocess:inst21.cpurd
RD => inst12.IN0
WR => spiprocess:inst21.cpuwr
WR => RAM_TEST:inst2.wrclock
ECS[2] => spiprocess:inst21.cpusel
ECS[2] => RAM_WR:inst.ecs
ECS[2] => RAM_RD:inst11.ecs
MISO => spiprocess:inst21.miso
RESET => spiprocess:inst21.reset
RFirq => spiprocess:inst21.RFirq
ADDR[0] => spiprocess:inst21.addr[0]
ADDR[0] => RAM_WR:inst.addr[0]
ADDR[0] => RAM_TEST:inst2.wraddress[0]
ADDR[0] => RAM_RD:inst11.addr[0]
ADDR[0] => RAM7:inst10.rdaddress[0]
ADDR[1] => spiprocess:inst21.addr[1]
ADDR[1] => RAM_WR:inst.addr[1]
ADDR[1] => RAM_TEST:inst2.wraddress[1]
ADDR[1] => RAM_RD:inst11.addr[1]
ADDR[1] => RAM7:inst10.rdaddress[1]
ADDR[2] => spiprocess:inst21.addr[2]
ADDR[2] => RAM_WR:inst.addr[2]
ADDR[2] => RAM_TEST:inst2.wraddress[2]
ADDR[2] => RAM_RD:inst11.addr[2]
ADDR[2] => RAM7:inst10.rdaddress[2]
ADDR[3] => spiprocess:inst21.addr[3]
ADDR[3] => RAM_WR:inst.addr[3]
ADDR[3] => RAM_TEST:inst2.wraddress[3]
ADDR[3] => RAM_RD:inst11.addr[3]
ADDR[3] => RAM7:inst10.rdaddress[3]
ADDR[4] => spiprocess:inst21.addr[4]
ADDR[4] => RAM_WR:inst.addr[4]
ADDR[4] => RAM_TEST:inst2.wraddress[4]
ADDR[4] => RAM_RD:inst11.addr[4]
ADDR[4] => RAM7:inst10.rdaddress[4]
ADDR[5] => spiprocess:inst21.addr[5]
ADDR[5] => RAM_WR:inst.addr[5]
ADDR[5] => RAM_TEST:inst2.wraddress[5]
ADDR[5] => RAM_RD:inst11.addr[5]
ADDR[5] => RAM7:inst10.rdaddress[5]
ADDR[6] => spiprocess:inst21.addr[6]
ADDR[6] => RAM_WR:inst.addr[6]
ADDR[6] => RAM_RD:inst11.addr[6]
ADDR[7] => spiprocess:inst21.addr[7]
ADDR[7] => RAM_WR:inst.addr[7]
ADDR[7] => RAM_RD:inst11.addr[7]
ADDR[8] => spiprocess:inst21.addr[8]
ADDR[8] => RAM_WR:inst.addr[8]
ADDR[8] => RAM_RD:inst11.addr[8]
ADDR[9] => spiprocess:inst21.addr[9]
ADDR[9] => RAM_WR:inst.addr[9]
ADDR[9] => RAM_RD:inst11.addr[9]
ADDR[10] => spiprocess:inst21.addr[10]
ADDR[10] => RAM_WR:inst.addr[10]
ADDR[10] => RAM_RD:inst11.addr[10]
ADDR[11] => spiprocess:inst21.addr[11]
ADDR[11] => RAM_WR:inst.addr[11]
ADDR[11] => RAM_RD:inst11.addr[11]
CPUOUTDATA[0] => spiprocess:inst21.cpuindata[0]
CPUOUTDATA[0] => RAM_TEST:inst2.data[0]
CPUOUTDATA[1] => spiprocess:inst21.cpuindata[1]
CPUOUTDATA[1] => RAM_TEST:inst2.data[1]
CPUOUTDATA[2] => spiprocess:inst21.cpuindata[2]
CPUOUTDATA[2] => RAM_TEST:inst2.data[2]
CPUOUTDATA[3] => spiprocess:inst21.cpuindata[3]
CPUOUTDATA[3] => RAM_TEST:inst2.data[3]
CPUOUTDATA[4] => spiprocess:inst21.cpuindata[4]
CPUOUTDATA[4] => RAM_TEST:inst2.data[4]
CPUOUTDATA[5] => spiprocess:inst21.cpuindata[5]
CPUOUTDATA[5] => RAM_TEST:inst2.data[5]
CPUOUTDATA[6] => spiprocess:inst21.cpuindata[6]
CPUOUTDATA[6] => RAM_TEST:inst2.data[6]
CPUOUTDATA[7] => spiprocess:inst21.cpuindata[7]
CPUOUTDATA[7] => RAM_TEST:inst2.data[7]
IRQ <= spiprocess:inst21.irq
CSN <= spiprocess:inst21.CSN
SCK <= spiprocess:inst21.SCK
CE <= spiprocess:inst21.CE
SFTEst <= TEST.DB_MAX_OUTPUT_PORT_TYPE
SFTEst1 <= Q[1].DB_MAX_OUTPUT_PORT_TYPE
CPUINDATA[0] <= MUX7:inst16.result[0]
CPUINDATA[1] <= MUX7:inst16.result[1]
CPUINDATA[2] <= MUX7:inst16.result[2]
CPUINDATA[3] <= MUX7:inst16.result[3]
CPUINDATA[4] <= MUX7:inst16.result[4]
CPUINDATA[5] <= MUX7:inst16.result[5]
CPUINDATA[6] <= MUX7:inst16.result[6]
CPUINDATA[7] <= MUX7:inst16.result[7]
|TEST|SPI:inst|spiprocess:inst21
clk => T_ReceivesomeData4.CLK
clk => ReceivesomeData.CLK
clk => T_ReceivesomeData6.CLK
clk => sendfinishtest~reg0.CLK
clk => mosi~reg0.CLK
clk => irq~reg0.CLK
clk => CSN~reg0.CLK
clk => SCK~reg0.CLK
clk => sendfilish.CLK
clk => StatusReg0[7].CLK
clk => StatusReg0[6].CLK
clk => StatusReg0[5].CLK
clk => StatusReg0[4].CLK
clk => StatusReg0[3].CLK
clk => StatusReg0[2].CLK
clk => StatusReg0[1].CLK
clk => StatusReg0[0].CLK
clk => ReadReging.CLK
clk => sendFinishByte[5].CLK
clk => sendFinishByte[4].CLK
clk => sendFinishByte[3].CLK
clk => sendFinishByte[2].CLK
clk => sendFinishByte[1].CLK
clk => sendFinishByte[0].CLK
clk => bitcounter[4].CLK
clk => bitcounter[3].CLK
clk => bitcounter[2].CLK
clk => bitcounter[1].CLK
clk => bitcounter[0].CLK
clk => senddata[7].CLK
clk => senddata[6].CLK
clk => senddata[5].CLK
clk => senddata[4].CLK
clk => senddata[3].CLK
clk => senddata[2].CLK
clk => senddata[1].CLK
clk => senddata[0].CLK
clk => ready.CLK
clk => ReceiveAddr[5]~reg0.CLK
clk => ReceiveAddr[4]~reg0.CLK
clk => ReceiveAddr[3]~reg0.CLK
clk => ReceiveAddr[2]~reg0.CLK
clk => ReceiveAddr[1]~reg0.CLK
clk => ReceiveAddr[0]~reg0.CLK
clk => SendAddr[5]~reg0.CLK
clk => SendAddr[4]~reg0.CLK
clk => SendAddr[3]~reg0.CLK
clk => SendAddr[2]~reg0.CLK
clk => SendAddr[1]~reg0.CLK
clk => SendAddr[0]~reg0.CLK
clk => ReceiveWen~reg0.CLK
clk => SendRDen~reg0.CLK
clk => senddatastart.CLK
clk => StatusReg1[7].CLK
clk => StatusReg1[6].CLK
clk => StatusReg1[5].CLK
clk => StatusReg1[4].CLK
clk => StatusReg1[3].CLK
clk => StatusReg1[2].CLK
clk => StatusReg1[1].CLK
clk => StatusReg1[0].CLK
clk => StatusReg2[7].CLK
clk => StatusReg2[6].CLK
clk => StatusReg2[5].CLK
clk => StatusReg2[4].CLK
clk => StatusReg2[3].CLK
clk => StatusReg2[2].CLK
clk => StatusReg2[1].CLK
clk => StatusReg2[0].CLK
clk => StatusReg3[7].CLK
clk => StatusReg3[6].CLK
clk => StatusReg3[5].CLK
clk => StatusReg3[4].CLK
clk => StatusReg3[3].CLK
clk => StatusReg3[2].CLK
clk => StatusReg3[1].CLK
clk => StatusReg3[0].CLK
clk => StatusReg4[7].CLK
clk => StatusReg4[6].CLK
clk => StatusReg4[5].CLK
clk => StatusReg4[4].CLK
clk => StatusReg4[3].CLK
clk => StatusReg4[2].CLK
clk => StatusReg4[1].CLK
clk => StatusReg4[0].CLK
clk => receiveByte[5].CLK
clk => receiveByte[4].CLK
clk => receiveByte[3].CLK
clk => receiveByte[2].CLK
clk => receiveByte[1].CLK
clk => receiveByte[0].CLK
clk => SendramCLK~reg0.CLK
clk => ramsendtemp[7].CLK
clk => ramsendtemp[6].CLK
clk => ramsendtemp[5].CLK
clk => ramsendtemp[4].CLK
clk => ramsendtemp[3].CLK
clk => ramsendtemp[2].CLK
clk => ramsendtemp[1].CLK
clk => ramsendtemp[0].CLK
clk => ramdReceivetemp[7].CLK
clk => ramdReceivetemp[6].CLK
clk => ramdReceivetemp[5].CLK
clk => ramdReceivetemp[4].CLK
clk => ramdReceivetemp[3].CLK
clk => ramdReceivetemp[2].CLK
clk => ramdReceivetemp[1].CLK
clk => ramdReceivetemp[0].CLK
clk => ReceiveCLK~reg0.CLK
clk => ReceiveData[7]~reg0.CLK
clk => ReceiveData[6]~reg0.CLK
clk => ReceiveData[5]~reg0.CLK
clk => ReceiveData[4]~reg0.CLK
clk => ReceiveData[3]~reg0.CLK
clk => ReceiveData[2]~reg0.CLK
clk => ReceiveData[1]~reg0.CLK
clk => ReceiveData[0]~reg0.CLK
cpurd => outdata[6]~reg0.CLK
cpurd => outdata[5]~reg0.CLK
cpurd => outdata[4]~reg0.CLK
cpurd => outdata[3]~reg0.CLK
cpurd => outdata[2]~reg0.CLK
cpurd => outdata[1]~reg0.CLK
cpurd => outdata[0]~reg0.CLK
cpurd => T_ReceivesomeData5.CLK
cpurd => outdata[7]~reg0.CLK
cpuwr => SendByteNum[4].CLK
cpuwr => SendByteNum[3].CLK
cpuwr => SendByteNum[2].CLK
cpuwr => SendByteNum[1].CLK
cpuwr => SendByteNum[0].CLK
cpuwr => senden.CLK
cpuwr => CE~reg0.CLK
cpuwr => SendByteNum[5].CLK
cpusel => CE~1.OUTPUTSELECT
cpusel => SendByteNum~6.OUTPUTSELECT
cpusel => SendByteNum~7.OUTPUTSELECT
cpusel => SendByteNum~8.OUTPUTSELECT
cpusel => SendByteNum~9.OUTPUTSELECT
cpusel => SendByteNum~10.OUTPUTSELECT
cpusel => SendByteNum~11.OUTPUTSELECT
cpusel => senden~1.OUTPUTSELECT
cpusel => outdata[6]~reg0.ENA
cpusel => outdata[5]~reg0.ENA
cpusel => outdata[4]~reg0.ENA
cpusel => outdata[3]~reg0.ENA
cpusel => outdata[2]~reg0.ENA
cpusel => outdata[1]~reg0.ENA
cpusel => outdata[0]~reg0.ENA
cpusel => outdata[7]~reg0.ENA
cpuindata[0] => CE~0.DATAB
cpuindata[0] => SendByteNum~5.DATAB
cpuindata[1] => SendByteNum~4.DATAB
cpuindata[2] => SendByteNum~3.DATAB
cpuindata[3] => SendByteNum~2.DATAB
cpuindata[4] => SendByteNum~1.DATAB
cpuindata[5] => SendByteNum~0.DATAB
cpuindata[6] => ~NO_FANOUT~
cpuindata[7] => ~NO_FANOUT~
ramindata[0] => senddata~7.DATAB
ramindata[0] => ramsendtemp~7.DATAB
ramindata[0] => ramsendtemp~31.DATAB
ramindata[1] => senddata~6.DATAB
ramindata[1] => ramsendtemp~6.DATAB
ramindata[1] => ramsendtemp~30.DATAB
ramindata[2] => senddata~5.DATAB
ramindata[2] => ramsendtemp~5.DATAB
ramindata[2] => ramsendtemp~29.DATAB
ramindata[3] => senddata~4.DATAB
ramindata[3] => ramsendtemp~4.DATAB
ramindata[3] => ramsendtemp~28.DATAB
ramindata[4] => senddata~3.DATAB
ramindata[4] => ramsendtemp~3.DATAB
ramindata[4] => ramsendtemp~27.DATAB
ramindata[5] => senddata~2.DATAB
ramindata[5] => ramsendtemp~2.DATAB
ramindata[5] => ramsendtemp~26.DATAB
ramindata[6] => senddata~1.DATAB
ramindata[6] => ramsendtemp~1.DATAB
ramindata[6] => ramsendtemp~25.DATAB
ramindata[7] => senddata~0.DATAB
ramindata[7] => ramsendtemp~0.DATAB
ramindata[7] => ramsendtemp~24.DATAB
outdata[0] <= outdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
outdata[1] <= outdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
outdata[2] <= outdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
outdata[3] <= outdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
outdata[4] <= outdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
outdata[5] <= outdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
outdata[6] <= outdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
outdata[7] <= outdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addr[0] => Equal0.IN23
addr[0] => Equal1.IN23
addr[0] => Equal2.IN23
addr[0] => Equal3.IN23
addr[0] => Equal4.IN23
addr[0] => Equal5.IN23
addr[0] => Equal6.IN23
addr[0] => Equal7.IN23
addr[0] => Equal8.IN23
addr[0] => Equal9.IN23
addr[0] => Equal10.IN23
addr[1] => Equal0.IN22
addr[1] => Equal1.IN22
addr[1] => Equal2.IN22
addr[1] => Equal3.IN22
addr[1] => Equal4.IN22
addr[1] => Equal5.IN22
addr[1] => Equal6.IN22
addr[1] => Equal7.IN22
addr[1] => Equal8.IN22
addr[1] => Equal9.IN22
addr[1] => Equal10.IN22
addr[2] => Equal0.IN21
addr[2] => Equal1.IN21
addr[2] => Equal2.IN21
addr[2] => Equal3.IN21
addr[2] => Equal4.IN21
addr[2] => Equal5.IN21
addr[2] => Equal6.IN21
addr[2] => Equal7.IN21
addr[2] => Equal8.IN21
addr[2] => Equal9.IN21
addr[2] => Equal10.IN21
addr[3] => Equal0.IN20
addr[3] => Equal1.IN20
addr[3] => Equal2.IN20
addr[3] => Equal3.IN20
addr[3] => Equal4.IN20
addr[3] => Equal5.IN20
addr[3] => Equal6.IN20
addr[3] => Equal7.IN20
addr[3] => Equal8.IN20
addr[3] => Equal9.IN20
addr[3] => Equal10.IN20
addr[4] => Equal0.IN19
addr[4] => Equal1.IN19
addr[4] => Equal2.IN19
addr[4] => Equal3.IN19
addr[4] => Equal4.IN19
addr[4] => Equal5.IN19
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