?? test.hier_info
字號:
addr[4] => Equal6.IN19
addr[4] => Equal7.IN19
addr[4] => Equal8.IN19
addr[4] => Equal9.IN19
addr[4] => Equal10.IN19
addr[5] => Equal0.IN18
addr[5] => Equal1.IN18
addr[5] => Equal2.IN18
addr[5] => Equal3.IN18
addr[5] => Equal4.IN18
addr[5] => Equal5.IN18
addr[5] => Equal6.IN18
addr[5] => Equal7.IN18
addr[5] => Equal8.IN18
addr[5] => Equal9.IN18
addr[5] => Equal10.IN18
addr[6] => Equal0.IN17
addr[6] => Equal1.IN17
addr[6] => Equal2.IN17
addr[6] => Equal3.IN17
addr[6] => Equal4.IN17
addr[6] => Equal5.IN17
addr[6] => Equal6.IN17
addr[6] => Equal7.IN17
addr[6] => Equal8.IN17
addr[6] => Equal9.IN17
addr[6] => Equal10.IN17
addr[7] => Equal0.IN16
addr[7] => Equal1.IN16
addr[7] => Equal2.IN16
addr[7] => Equal3.IN16
addr[7] => Equal4.IN16
addr[7] => Equal5.IN16
addr[7] => Equal6.IN16
addr[7] => Equal7.IN16
addr[7] => Equal8.IN16
addr[7] => Equal9.IN16
addr[7] => Equal10.IN16
addr[8] => Equal0.IN15
addr[8] => Equal1.IN15
addr[8] => Equal2.IN15
addr[8] => Equal3.IN15
addr[8] => Equal4.IN15
addr[8] => Equal5.IN15
addr[8] => Equal6.IN15
addr[8] => Equal7.IN15
addr[8] => Equal8.IN15
addr[8] => Equal9.IN15
addr[8] => Equal10.IN15
addr[9] => Equal0.IN14
addr[9] => Equal1.IN14
addr[9] => Equal2.IN14
addr[9] => Equal3.IN14
addr[9] => Equal4.IN14
addr[9] => Equal5.IN14
addr[9] => Equal6.IN14
addr[9] => Equal7.IN14
addr[9] => Equal8.IN14
addr[9] => Equal9.IN14
addr[9] => Equal10.IN14
addr[10] => Equal0.IN13
addr[10] => Equal1.IN13
addr[10] => Equal2.IN13
addr[10] => Equal3.IN13
addr[10] => Equal4.IN13
addr[10] => Equal5.IN13
addr[10] => Equal6.IN13
addr[10] => Equal7.IN13
addr[10] => Equal8.IN13
addr[10] => Equal9.IN13
addr[10] => Equal10.IN13
addr[11] => Equal0.IN12
addr[11] => Equal1.IN12
addr[11] => Equal2.IN12
addr[11] => Equal3.IN12
addr[11] => Equal4.IN12
addr[11] => Equal5.IN12
addr[11] => Equal6.IN12
addr[11] => Equal7.IN12
addr[11] => Equal8.IN12
addr[11] => Equal9.IN12
addr[11] => Equal10.IN12
mosi <= mosi~reg0.DB_MAX_OUTPUT_PORT_TYPE
miso => StatusReg0~0.DATAB
miso => StatusReg0~1.DATAB
miso => StatusReg0~2.DATAB
miso => StatusReg0~3.DATAB
miso => StatusReg0~4.DATAB
miso => StatusReg0~5.DATAB
miso => StatusReg0~6.DATAB
miso => StatusReg0~7.DATAB
miso => StatusReg0~24.DATAB
miso => StatusReg0~25.DATAB
miso => StatusReg0~26.DATAB
miso => StatusReg0~27.DATAB
miso => StatusReg0~28.DATAB
miso => StatusReg0~29.DATAB
miso => StatusReg0~30.DATAB
miso => StatusReg0~31.DATAB
miso => Selector53.IN3
miso => ramdReceivetemp~32.DATAB
reset => mosi~7.OUTPUTSELECT
reset => irq~0.OUTPUTSELECT
reset => CSN~9.OUTPUTSELECT
reset => SCK~7.OUTPUTSELECT
reset => sendfilish~8.OUTPUTSELECT
reset => StatusReg0~72.OUTPUTSELECT
reset => StatusReg0~73.OUTPUTSELECT
reset => StatusReg0~74.OUTPUTSELECT
reset => StatusReg0~75.OUTPUTSELECT
reset => StatusReg0~76.OUTPUTSELECT
reset => StatusReg0~77.OUTPUTSELECT
reset => StatusReg0~78.OUTPUTSELECT
reset => StatusReg0~79.OUTPUTSELECT
reset => sendFinishByte~60.OUTPUTSELECT
reset => sendFinishByte~61.OUTPUTSELECT
reset => sendFinishByte~62.OUTPUTSELECT
reset => sendFinishByte~63.OUTPUTSELECT
reset => sendFinishByte~64.OUTPUTSELECT
reset => sendFinishByte~65.OUTPUTSELECT
reset => bitcounter~41.OUTPUTSELECT
reset => bitcounter~42.OUTPUTSELECT
reset => bitcounter~43.OUTPUTSELECT
reset => bitcounter~44.OUTPUTSELECT
reset => bitcounter~45.OUTPUTSELECT
reset => senddata~72.OUTPUTSELECT
reset => senddata~73.OUTPUTSELECT
reset => senddata~74.OUTPUTSELECT
reset => senddata~75.OUTPUTSELECT
reset => senddata~76.OUTPUTSELECT
reset => senddata~77.OUTPUTSELECT
reset => senddata~78.OUTPUTSELECT
reset => senddata~79.OUTPUTSELECT
reset => ready~8.OUTPUTSELECT
reset => ReceiveAddr~36.OUTPUTSELECT
reset => ReceiveAddr~37.OUTPUTSELECT
reset => ReceiveAddr~38.OUTPUTSELECT
reset => ReceiveAddr~39.OUTPUTSELECT
reset => ReceiveAddr~40.OUTPUTSELECT
reset => ReceiveAddr~41.OUTPUTSELECT
reset => SendAddr~48.OUTPUTSELECT
reset => SendAddr~49.OUTPUTSELECT
reset => SendAddr~50.OUTPUTSELECT
reset => SendAddr~51.OUTPUTSELECT
reset => SendAddr~52.OUTPUTSELECT
reset => SendAddr~53.OUTPUTSELECT
reset => SendByteNum~15.OUTPUTSELECT
reset => SendByteNum~14.OUTPUTSELECT
reset => SendByteNum~13.OUTPUTSELECT
reset => ReceiveWen~7.OUTPUTSELECT
reset => SendRDen~6.OUTPUTSELECT
reset => senddatastart~6.OUTPUTSELECT
reset => SendByteNum~12.OUTPUTSELECT
reset => SendByteNum~16.OUTPUTSELECT
reset => SendByteNum~17.OUTPUTSELECT
reset => senden~2.OUTPUTSELECT
reset => CE~2.OUTPUTSELECT
reset => T_ReceivesomeData4~1.OUTPUTSELECT
reset => ReceivesomeData~2.OUTPUTSELECT
reset => T_ReceivesomeData6~2.OUTPUTSELECT
reset => sendfinishtest~0.OUTPUTSELECT
reset => ReadReging.ENA
reset => StatusReg1[7].ENA
reset => StatusReg1[6].ENA
reset => StatusReg1[5].ENA
reset => StatusReg1[4].ENA
reset => StatusReg1[3].ENA
reset => StatusReg1[2].ENA
reset => StatusReg1[1].ENA
reset => StatusReg1[0].ENA
reset => StatusReg2[7].ENA
reset => StatusReg2[6].ENA
reset => StatusReg2[5].ENA
reset => StatusReg2[4].ENA
reset => StatusReg2[3].ENA
reset => StatusReg2[2].ENA
reset => StatusReg2[1].ENA
reset => StatusReg2[0].ENA
reset => StatusReg3[7].ENA
reset => StatusReg3[6].ENA
reset => StatusReg3[5].ENA
reset => StatusReg3[4].ENA
reset => StatusReg3[3].ENA
reset => StatusReg3[2].ENA
reset => StatusReg3[1].ENA
reset => StatusReg3[0].ENA
reset => StatusReg4[7].ENA
reset => StatusReg4[6].ENA
reset => StatusReg4[5].ENA
reset => StatusReg4[4].ENA
reset => StatusReg4[3].ENA
reset => StatusReg4[2].ENA
reset => StatusReg4[1].ENA
reset => StatusReg4[0].ENA
irq <= irq~reg0.DB_MAX_OUTPUT_PORT_TYPE
CSN <= CSN~reg0.DB_MAX_OUTPUT_PORT_TYPE
SCK <= SCK~reg0.DB_MAX_OUTPUT_PORT_TYPE
RFirq => irq~0.DATAA
RFirq => T_ReceivesomeData2.CLK
SendAddr[0] <= SendAddr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SendAddr[1] <= SendAddr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SendAddr[2] <= SendAddr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SendAddr[3] <= SendAddr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SendAddr[4] <= SendAddr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SendAddr[5] <= SendAddr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SendRDen <= SendRDen~reg0.DB_MAX_OUTPUT_PORT_TYPE
ReceiveData[0] <= ReceiveData[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ReceiveData[1] <= ReceiveData[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ReceiveData[2] <= ReceiveData[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ReceiveData[3] <= ReceiveData[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ReceiveData[4] <= ReceiveData[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ReceiveData[5] <= ReceiveData[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ReceiveData[6] <= ReceiveData[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ReceiveData[7] <= ReceiveData[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ReceiveAddr[0] <= ReceiveAddr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ReceiveAddr[1] <= ReceiveAddr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ReceiveAddr[2] <= ReceiveAddr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ReceiveAddr[3] <= ReceiveAddr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ReceiveAddr[4] <= ReceiveAddr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ReceiveAddr[5] <= ReceiveAddr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SendramCLK <= SendramCLK~reg0.DB_MAX_OUTPUT_PORT_TYPE
ReceiveCLK <= ReceiveCLK~reg0.DB_MAX_OUTPUT_PORT_TYPE
ReceiveWen <= ReceiveWen~reg0.DB_MAX_OUTPUT_PORT_TYPE
CE <= CE~reg0.DB_MAX_OUTPUT_PORT_TYPE
sendfinishtest <= sendfinishtest~reg0.DB_MAX_OUTPUT_PORT_TYPE
|TEST|SPI:inst|RAM_TEST:inst2
data[0] => data[0]~7.IN1
data[1] => data[1]~6.IN1
data[2] => data[2]~5.IN1
data[3] => data[3]~4.IN1
data[4] => data[4]~3.IN1
data[5] => data[5]~2.IN1
data[6] => data[6]~1.IN1
data[7] => data[7]~0.IN1
rdaddress[0] => rdaddress[0]~5.IN1
rdaddress[1] => rdaddress[1]~4.IN1
rdaddress[2] => rdaddress[2]~3.IN1
rdaddress[3] => rdaddress[3]~2.IN1
rdaddress[4] => rdaddress[4]~1.IN1
rdaddress[5] => rdaddress[5]~0.IN1
rdclock => rdclock~0.IN1
rden => rden~0.IN1
wraddress[0] => wraddress[0]~5.IN1
wraddress[1] => wraddress[1]~4.IN1
wraddress[2] => wraddress[2]~3.IN1
wraddress[3] => wraddress[3]~2.IN1
wraddress[4] => wraddress[4]~1.IN1
wraddress[5] => wraddress[5]~0.IN1
wrclock => wrclock~0.IN1
wren => wren~0.IN1
q[0] <= altdpram:altdpram_component.q
q[1] <= altdpram:altdpram_component.q
q[2] <= altdpram:altdpram_component.q
q[3] <= altdpram:altdpram_component.q
q[4] <= altdpram:altdpram_component.q
q[5] <= altdpram:altdpram_component.q
q[6] <= altdpram:altdpram_component.q
q[7] <= altdpram:altdpram_component.q
|TEST|SPI:inst|RAM_TEST:inst2|altdpram:altdpram_component
data[0] => cells[63][0].DATAIN
data[0] => cells[62][0].DATAIN
data[0] => cells[61][0].DATAIN
data[0] => cells[60][0].DATAIN
data[0] => cells[59][0].DATAIN
data[0] => cells[58][0].DATAIN
data[0] => cells[57][0].DATAIN
data[0] => cells[56][0].DATAIN
data[0] => cells[55][0].DATAIN
data[0] => cells[54][0].DATAIN
data[0] => cells[53][0].DATAIN
data[0] => cells[52][0].DATAIN
data[0] => cells[51][0].DATAIN
data[0] => cells[50][0].DATAIN
data[0] => cells[49][0].DATAIN
data[0] => cells[48][0].DATAIN
data[0] => cells[47][0].DATAIN
data[0] => cells[46][0].DATAIN
data[0] => cells[45][0].DATAIN
data[0] => cells[44][0].DATAIN
data[0] => cells[43][0].DATAIN
data[0] => cells[42][0].DATAIN
data[0] => cells[41][0].DATAIN
data[0] => cells[40][0].DATAIN
data[0] => cells[39][0].DATAIN
data[0] => cells[38][0].DATAIN
data[0] => cells[37][0].DATAIN
data[0] => cells[36][0].DATAIN
data[0] => cells[35][0].DATAIN
data[0] => cells[34][0].DATAIN
data[0] => cells[33][0].DATAIN
data[0] => cells[32][0].DATAIN
data[0] => cells[31][0].DATAIN
data[0] => cells[30][0].DATAIN
data[0] => cells[29][0].DATAIN
data[0] => cells[28][0].DATAIN
data[0] => cells[27][0].DATAIN
data[0] => cells[26][0].DATAIN
data[0] => cells[25][0].DATAIN
data[0] => cells[24][0].DATAIN
data[0] => cells[23][0].DATAIN
data[0] => cells[22][0].DATAIN
data[0] => cells[21][0].DATAIN
data[0] => cells[20][0].DATAIN
data[0] => cells[19][0].DATAIN
data[0] => cells[18][0].DATAIN
data[0] => cells[17][0].DATAIN
data[0] => cells[16][0].DATAIN
data[0] => cells[15][0].DATAIN
data[0] => cells[14][0].DATAIN
data[0] => cells[13][0].DATAIN
data[0] => cells[12][0].DATAIN
data[0] => cells[11][0].DATAIN
data[0] => cells[10][0].DATAIN
data[0] => cells[9][0].DATAIN
data[0] => cells[8][0].DATAIN
data[0] => cells[7][0].DATAIN
data[0] => cells[6][0].DATAIN
data[0] => cells[5][0].DATAIN
data[0] => cells[4][0].DATAIN
data[0] => cells[3][0].DATAIN
data[0] => cells[2][0].DATAIN
data[0] => cells[1][0].DATAIN
data[0] => cells[0][0].DATAIN
data[1] => cells[63][1].DATAIN
data[1] => cells[62][1].DATAIN
data[1] => cells[61][1].DATAIN
data[1] => cells[60][1].DATAIN
data[1] => cells[59][1].DATAIN
data[1] => cells[58][1].DATAIN
data[1] => cells[57][1].DATAIN
data[1] => cells[56][1].DATAIN
data[1] => cells[55][1].DATAIN
data[1] => cells[54][1].DATAIN
data[1] => cells[53][1].DATAIN
data[1] => cells[52][1].DATAIN
data[1] => cells[51][1].DATAIN
data[1] => cells[50][1].DATAIN
data[1] => cells[49][1].DATAIN
data[1] => cells[48][1].DATAIN
data[1] => cells[47][1].DATAIN
data[1] => cells[46][1].DATAIN
data[1] => cells[45][1].DATAIN
data[1] => cells[44][1].DATAIN
data[1] => cells[43][1].DATAIN
data[1] => cells[42][1].DATAIN
data[1] => cells[41][1].DATAIN
data[1] => cells[40][1].DATAIN
data[1] => cells[39][1].DATAIN
data[1] => cells[38][1].DATAIN
data[1] => cells[37][1].DATAIN
data[1] => cells[36][1].DATAIN
data[1] => cells[35][1].DATAIN
data[1] => cells[34][1].DATAIN
data[1] => cells[33][1].DATAIN
data[1] => cells[32][1].DATAIN
data[1] => cells[31][1].DATAIN
data[1] => cells[30][1].DATAIN
data[1] => cells[29][1].DATAIN
data[1] => cells[28][1].DATAIN
data[1] => cells[27][1].DATAIN
data[1] => cells[26][1].DATAIN
data[1] => cells[25][1].DATAIN
data[1] => cells[24][1].DATAIN
data[1] => cells[23][1].DATAIN
data[1] => cells[22][1].DATAIN
data[1] => cells[21][1].DATAIN
data[1] => cells[20][1].DATAIN
data[1] => cells[19][1].DATAIN
data[1] => cells[18][1].DATAIN
data[1] => cells[17][1].DATAIN
data[1] => cells[16][1].DATAIN
data[1] => cells[15][1].DATAIN
data[1] => cells[14][1].DATAIN
data[1] => cells[13][1].DATAIN
data[1] => cells[12][1].DATAIN
data[1] => cells[11][1].DATAIN
data[1] => cells[10][1].DATAIN
data[1] => cells[9][1].DATAIN
data[1] => cells[8][1].DATAIN
data[1] => cells[7][1].DATAIN
data[1] => cells[6][1].DATAIN
data[1] => cells[5][1].DATAIN
data[1] => cells[4][1].DATAIN
data[1] => cells[3][1].DATAIN
data[1] => cells[2][1].DATAIN
data[1] => cells[1][1].DATAIN
data[1] => cells[0][1].DATAIN
data[2] => cells[63][2].DATAIN
data[2] => cells[62][2].DATAIN
data[2] => cells[61][2].DATAIN
data[2] => cells[60][2].DATAIN
data[2] => cells[59][2].DATAIN
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