?? and5or2.stx
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Release 5.1i - xst F.23Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.--> Parameter TMPDIR set to .CPU : 0.00 / 0.42 s | Elapsed : 0.00 / 1.00 s --> =========================================================================* HDL Compilation *=========================================================================Compiling source file "and5or2.sprj"Compiling include file "and5or2.vf"Module <and5or2> compiledCompiling include file "J:/eda/Xilinx/verilog/src/iSE/unisim_comp.v"No errors in compilationAnalysis of file <and5or2.sprj> succeeded.CPU : 0.67 / 1.09 s | Elapsed : 0.00 / 1.00 s --> Total memory usage is 52080 kilobytes
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