Release 5.1i - xst F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to .CPU : 0.00 / 1.07 s | Elapsed : 0.00 / 1.00 s --> =========================================================================*                          HDL Compilation                              *=========================================================================Compiling source file "andnor2_p.sprj"Compiling include file "andnor2_p.vf"Module <andnor2_p> compiledCompiling include file "J:/eda/Xilinx/verilog/src/iSE/unisim_comp.v"No errors in compilationAnalysis of file <andnor2_p.sprj> succeeded.CPU : 0.81 / 1.88 s | Elapsed : 0.00 / 1.00 s --> Total memory usage is 52080 kilobytes