Release 6.2i Par G.30Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.LATTICE-WESTOR::  Tue Oct 12 22:27:25 2004C:/eda/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 mode7cnt_map.ncd
mode7cnt.ncd mode7cnt.pcf Constraints file: mode7cnt.pcfLoading device database for application Par from file "mode7cnt_map.ncd".   "mode7cnt" is an NCD, version 2.38, device xcv50e, package cs144, speed -8Loading device for application Par from file 'v50e.nph' in environment
C:/eda/Xilinx.Device speed data version:  PRODUCTION 1.69 2003-12-13.Device utilization summary:   Number of External GCLKIOBs         1 out of 4      25%   Number of External IOBs             3 out of 94      3%      Number of LOCed External IOBs    0 out of 3       0%   Number of SLICEs                    2 out of 768     1%   Number of GCLKs                     1 out of 4      25%Overall effort level (-ol):   Standard (set by user)Placer effort level (-pl):    Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl):    Standard (set by user)Phase 1.1Phase 1.1 (Checksum:98969b) REAL time: 0 secs Phase 2.23Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs Phase 3.3Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8.Phase 5.8 (Checksum:989d87) REAL time: 0 secs Phase 6.5Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file mode7cnt.ncd.Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 15 unrouted;       REAL time: 0 secs Phase 2: 13 unrouted;       REAL time: 0 secs Phase 3: 2 unrouted;       REAL time: 0 secs Phase 4: 0 unrouted;       REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics.**************************Generating Clock Report**************************+----------------------------+----------+--------+------------+-------------+|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|+----------------------------+----------+--------+------------+-------------+|         clk_BUFGP          |  Global  |    2   |  0.000     |  0.287      |+----------------------------+----------+--------+------------+-------------+   The Delay Summary Report   The SCORE FOR THIS DESIGN is: 43The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0   The AVERAGE CONNECTION DELAY for this design is:        0.396   The MAXIMUM PIN DELAY IS:                               0.555   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   0.183   Listing Pin Delays by value: (nsec)    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00   ---------   ---------   ---------   ---------   ---------   ---------          15           0           0           0           0           0Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 0 secs Total CPU time to PAR completion: 0 secs Peak Memory Usage:  45 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Writing design to file mode7cnt.ncd.PAR done.