// Verilog model created from and4or2.sch - Tue Oct 12 22:27:16 2004

`timescale 1ns / 1ps

module and4or2(in1, in2, in3, in4, out_t);

    input in1;
    input in2;
    input in3;
    input in4;
   output out_t;
   
   wire XLXN_7;
   wire XLXN_8;
   
   AND2 XLXI_1 (.I0(in2), .I1(in1), .O(XLXN_7));
   AND2 XLXI_2 (.I0(in4), .I1(in3), .O(XLXN_8));
   OR2 XLXI_3 (.I0(XLXN_8), .I1(XLXN_7), .O(out_t));
endmodule