// Verilog model created from fdq.sch - Tue Oct 12 22:27:15 2004

`timescale 1ns / 1ps

module fdq(clk, Din, Q, Qo);

    input clk;
    input Din;
   output Q;
   output Qo;
   
   
   FD XLXI_1 (.C(clk), .D(Din), .Q(Q));
   // synthesis attribute INIT of XLXI_1 is "0"
   // synopsys translate_off
   defparam XLXI_1.INIT = 1'b0;
   // synopsys translate_on
   INV XLXI_2 (.I(Q), .O(Qo));
endmodule