Release 5.1i - xst F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to .CPU : 0.00 / 1.16 s | Elapsed : 0.00 / 1.00 s --> =========================================================================*                          HDL Compilation                              *=========================================================================Compiling source file "and4or2.sprj"Compiling include file "and4or2.vf"Module <and4or2> compiledCompiling include file "J:/eda/Xilinx/verilog/src/iSE/unisim_comp.v"No errors in compilationAnalysis of file <and4or2.sprj> succeeded.CPU : 0.78 / 1.94 s | Elapsed : 0.00 / 1.00 s --> Total memory usage is 52080 kilobytes